Hi,I'm a bit lost concerning the functional differences between these two systems. Is there a comprehensive comparision somewhere? What does Modelsim offer that Quartus doesn't? And is there a significant difference bewteen Modelsim Web Ed. and Modelsim ALtera full? Thx, Fried
You can use test benches with ModelSim but not with the Quartus native simulator.http://www.altera.com/products/software/products/model/eda-ms.html has a comparison chart for ModelSim-Altera Edition versus ModelSim-Altera Web Edition.
The quartus simulator is quick to set up and useful for simulating design blocks that are fairly simple, have smallish number of inputs (and these inputs are basic to create, ie. not complicated 32bit buses) and the simulation time is short.If this is not the case then you could spend a long time either setting up the simulation or actually doing the simulation. This is where Modelsim is great, its much faster at doing simulations of large designs (and/or long simulations) and you can incorporate testbenching for complicated input sets.
One of the biggest differences between the Q2 simulator and Any of the simulation tools using testbench files is that you can design your testbench file to react to outputs from the Unit Under Test. In other words the testbench can simulate the devices the FPGA is connected to. Years ago I had to design my Q2 sims by running them for an amount of time, seeing the output change and note the point it does, modify the sim input to react to the change then run till the next change. Now I just write the responses into the testbench and only change it when the testbench is wrong.
--- Quote Start --- One of the biggest differences between the Q2 simulator and Any of the simulation tools using testbench files is that you can design your testbench file to react to outputs from the Unit Under Test. --- Quote End --- So Bob, what is the difference between the wvf file and a generic Verilog test bench? I opened one of the wvf files and it is a simple text file. I also noticed that Q2 simulator asks for "test" file, and by definition one must provide a wvf file as an input to the simulation. That is where I get confused? Thx
I think it should be vwf not wvf. :) Yes, you're right. The vwf file is a text file which contains a set of input stimulus into your design. When you run the simulator, it takes in this input stimulus and display the results in the waveform. It has it's own format and it only can be used by QII Simulator. That's why running QII simulator requires the vwf. You have to view the waveform to see the result.As for Verilog test bench, it is also a text file but is written in the Verilog language. Using the verilog language, you can write the input stimulus as well. Not only write input stimulus, you can do more than that (e.g. write a checker and verify your simulation results without viewing the waveform and etc). Basically writting testbench has a lot of flexiblity over the vwf. It is a language by itself unlike vwf contains just only the plain data (input stimulus). The tesbench you write is also generic which normally can be used by all third party simulation tools (e.g. Modelsim, VCS, NC-Sim). Hope it helps.