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Moving pin on PCIe HARD IP to another location

BS11
Beginner
638 Views

Hi,

 

I am trying to move the pin location of the channel 0 RX/TX to a different location.  They are both in the PCIE HARD IP pin designations.  I see the following error below but cannot find any constraints in the .qsf or .sdc file that would keep the reassignment from happening.  Can anyone shine some light on the error below?  Are the pins in the design so locked in stone that you can't even reassign them inside the PCIe HARD IP Block?

 

FYI - The design compiled before I changed the pin assignment

 

Part: Stratix V 5SGXMA4K3F40C3

Tool:  Quartus Prime Standard Edition 18.1

Example Design Used: Avalon Memory-Mapped Interface with with DMA (Stratix V Hard IP for PCI Express)

 

Remapping in Assignment Editor:

hip_serial_tx_out0         --- AU37 Reassigned to U37

hip_serial_tx_out0(n)    --- AU36 Reassigned to U36

hip_serial_rx_in0           --- AV38 Reassigned to V38

hip_serial_rx_in0(n)      --- AV39 Reassigned to V39

 

Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 Receiver channel(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.

Error (175020): The Fitter cannot place logic Receiver channel that is part of V-Series Avalon-MM DMA for PCI Express Intel FPGA IP altpcie_256_hip_avmm_hwtcl in region (0, 53) to (0, 55), to which it is constrained, because there are no valid locations in the region for logic of this type.

 

Info (14596): Information about the failing component(s):
Info (175028): The Receiver channel name(s): hip_serial_rx_in0
Info (175015): The I/O pad hip_serial_rx_in0 is constrained to the location PIN_V38 due to: User Location Constraints (PIN_V38)
Info (14709): The constrained I/O pad is contained within a pin, which is contained within this Receiver channel

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6 Replies
wchiah
Employee
613 Views

Hi,


Thank you for reaching out.

Just to let you know that Intel has received your support request and I am assigned to work on it.

Allow me some time to look into your issue. I shall come back to you with findings.


Thank you for your patience.


Best regards,

Wincent_C_Intel


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wchiah
Employee
604 Views

Hi,

 

  1. Why would you reassign the pin location? is there any specific reason for doing that?
  2. Is the design able to run well before you change the pin location?

 

Can you please check the IO pins and clock is compact to the Stratix V IO user guidelines.

And also check by mistake using the transceiver pins. If using the transceiver pins , the above error might possible occur.

 

Regards,

Wincent_C_Intel

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BS11
Beginner
592 Views

Hi,

 

The design has no problem compiling in it’s original form.  We have a box from an old design where the pins need to be reassigned to work with the connectors.  I am trying to prove a few things:

 

  1. We can reassign pins between different channels in the PCIe HARD IP.  It seems that we should be able to do so.

 

Once I can establish that 1 is possible then I will attempt 2 below:

 

  1. Reassign the hip serial TX/RX pins to a non-PCIE HARD IP location to see if I can compile the design.  I am attempting this to prove whether this is possible due to the previous design. 

 

 

Your Question: And also check by mistake using the transceiver pins. If using the transceiver pins , the above error might possible occur.

 

I’ve checked the transceiver pins and am reassigning to the pins in GXB_TX_L10 from GXB_TX_L0 for the 5SGXMA4K3F40C3 part.  These pin locations should be correct.  Locations are taken directly from Pin planner PCIe HARD IP diagram for the part listed(shown under heading “Pin Location” on spreadsheet snip below).

 

Remapping in Assignment Editor:

hip_serial_tx_out0         --- AU37 Reassigned to U37

hip_serial_tx_out0(n)    --- AU36 Reassigned to U36

hip_serial_rx_in0           --- AV38 Reassigned to V38

hip_serial_rx_in0(n)      --- AV39 Reassigned to V39

 

 

BS11_0-1656336880116.png

 

 

 

Your Question: Can you please check the IO pins and clock is compact to the Stratix V IO user guidelines.

Not sure what you’re asking here.  Can you please restate your question?

 

Thanks,

 

Bryan

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wchiah
Employee
568 Views

Hi,


Let me suggest this, 

  • it could be a problem with the FPGA not being configured before the host system starts to enumerate the PCIe. To test this theory, you could bring the system up, program the FPGA, then reboot the system without cycling power (Ctrl-Alt-Del on Windows machines).
  • Or you could externally power the dev board, configure the FPGA, then power up the system.
  •  In either case, if the system then sees the card, you know it's just the configuration time.
  • If it still doesn't work, I would then hook up the Signaltap with the LTSSM as described in the Debugging section of the user guide.


Looking forward to hear back from you.

Regards,

Wincent_Intel_C


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wchiah
Employee
545 Views

Hi,

I wish to follow up with you on this case, so do you have any further question on this ?

Regards,

Wincent_C_Intel


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wchiah
Employee
530 Views

Hi,


We do not receive any response from you to the previous answer that I have provided.

This thread will be transitioned to community support. If you have a new question,

feel free to open a new thread to get support from Intel experts.

Otherwise, the community users will continue to help you on this thread. Thank you


Regards,

Wincent_Intel


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