Multiple clock problem ？

[Altera_Forum]

i am sorry disturb you again , but i have a quartus about multiple CLOCK ,can you have a suggest to solve it ， 

 i use EP3C5,and it only have two PLLS. and the soft is quaruts10.0   here is my code :  module dso_pll(clkin0,clkin1,clr,  ad_clk0,ad_clk180,ad_clk90,ad_clk270,  ad_clk45,ad_clk135,ad_clk225,ad_clk315,  clk0,clk180,clk90,clk270,  spll1,    clk45,clk135,clk225,clk315);    input clkin0,clkin1,spll1;  output ad_clk0,ad_clk180,ad_clk90,ad_clk270; // clk for ad//  output clk0,clk180,clk90,clk270,clk100b;/// sample for AD///  output ad_clk45,ad_clk135,ad_clk225,ad_clk315;// clk for ad//  output clk45,clk135,clk225,clk315;/// sample for AD9288/    wire clk0,clk45,clk90,clk135,clk180,clk225,clk315,clk270;    wire ad_clk0,ad_clk180,ad_clk90,ad_clk270;  wire ad_clk45,ad_clk135,ad_clk225,ad_clk315;   wire clk125_0,clk125_45,clk125_90,clk125_135,  clk0_100,clk45_100,clk90_100,clk135_100;   pll0 pll0_inst(.inclk0(clkin0),  .c0(clk125_0),.c1(clk125_45), ///125m  .c2(clk125_90),.c3(clk125_135));    pll1 pll1_inst(.inclk0(clkin1),.c0(clk0_100),.c1(clk45_100),  .c2(clk90_100),.c3(clk135_100));//100m     assign ad_clk0 = clk0 ; assign ad_clk90 = clk90 ; assign ad_clk180 = clk180 ; assign ad_clk270 = clk270 ; assign ad_clk45 = clk45 ; assign ad_clk225 = clk225 ; assign ad_clk135 = clk135 ; assign ad_clk315 = clk315 ;  assign clk0 = spll1 ? clk125_0 : clk0_100; assign clk45 = spll1 ? clk125_45 : clk45_100; assign clk90 = spll1 ? clk125_90 : clk90_100; assign clk135 = spll1 ? clk125_135 : clk135_100;  assign clk180 = spll1 ? (!clk125_0) : (!clk0_100); assign clk225 = spll1 ? (!clk125_45) : (!clk45_100);  assign clk270 = spll1 ? (!clk125_90) : (!clk90_100);  assign clk315 = spll1 ? (!clk125_135) : (!clk135_100); endmodule  :: clk0 .clk45,clk90,clk135,clk180,clk225,clk270,clk315 is used for FPGA which is used to sample for Ad_data.  :: AD_CLK0,AD_CLK45,AD_CLK90,AD_CLK135,AD_CLK225,AD_CLK270.AD_CLK315 is provided for AD   :: the clk125_0 is 125M and phase is 0, :: the clk125_45 is 125M and phase is 45, :: the clk125_90 is 125M and phase is 90, :: the clk125_135 is 125M and phase is135, :: the clk125_180 is 125M and phase is 180, :: the clk125_225 is 125M and phase is 225, :: the clk125_270 is 125M and phase is 270, :: the clk125_315 is 125M and phase is 315,  such as clk0_100 , but clk0_100 is 100M .  then i have a quartus is that   1 ： how i make sure that Length of time form ad_clk0 to outpin ,and from ad_clk90 to output pin , ... is equivalent。 2 : when the clk is 125M, and i make the PLL0 phase is "0,45,90,135 " ,but i measure the ADCLK output pin ,then i find that  ad_clk0 -> ad_clk45 : 1050ps , ad_clk45 -> ad_clk90 : 500ps . ........ then i have quartus that how i can make sure the length of time is equivalent . thank you very much

[Altera_Forum]

You're using logic to mux the clk125_* and clk125. This will add large and varying delays to the clock. 

Try using ALTCLKCTRL blocks instead.

[Altera_Forum]

OK，thank you, i try again .

[Altera_Forum]

--- Quote Start ---  You're using logic to mux the clk125_* and clk125. This will add large and varying delays to the clock. Try using ALTCLKCTRL blocks instead.  --- Quote End ---   i am sorry to trouble you again ,can you help me ?  when i use the clkctrl IP core ,then it is error :  the error is that the clkctrl is cannot drive by two plls , so i cannot use clkctrl ,  then can you give me a reference for multiple clock ?  thank you very much..

[Altera_Forum]

Can you rephrase that? 

Is the error that atlclkctrl cannot drive two PLLs? Or is the error that altclkcltr cannot be driven by two PLLs?

[Altera_Forum]

i am sorry my english is poor , 

the error is that the altclkctrl cannot be driven by two PLLS  so can you give a advise ?  thank you very much

[Altera_Forum]

--- Quote Start ---  Can you rephrase that? Is the error that atlclkctrl cannot drive two PLLs? Or is the error that altclkcltr cannot be driven by two PLLs?  --- Quote End ---    i am sorry my english is poor ,  the error is that the altclkctrl cannot be driven by two PLLS  so can you give a advise ?  thank you very much

[Altera_Forum]

please paste the error here

[Altera_Forum]

--- Quote Start ---  please paste the error here  --- Quote End ---    OK， the down is my code for clkctrl_cs clkctrl_cs clkctrl_cs1(.clkselect(spll1) ,.inclk0x(clk0_100) , .inclk1x(clk125_0) ,.outclk(clk0)) ; ............... clkctrl_cs clkctrl_cs8(.clkselect(spll1) ,.inclk0x(clk315_100) ,.inclk1x(clk125_315) ,.outclk(clk315)) ;  and the down is the error   Error: inclk port of Clock Control Block   Error: inclk port of Clock Control Block "dso_pll:ll_inst|clkctrl_cs:clkctrl_cs4|clkctrl_cs_altclkctrl_uhi:clkctrl_cs_altclkctrl_uhi_component|clkctrl1" must be driven by 1 PLLs but is driven by 2 PLLs  Info: Clock Control Block is driven by PLL "dso_pll:ll_inst|pll1:ll1_inst|altpll:altpll_component|pll1_altpll:auto_generated|pll1"  Info: Clock Control Block is driven by PLL "dso_pll:ll_inst|pll0:ll0_inst|altpll:altpll_component|altpll_km93:auto_generated|pll1"  Error: Port(s) inclk[0] or inclk[1] of Clock Control Block "dso_pll:ll_inst|clkctrl_cs:clkctrl_cs5|clkctrl_cs_altclkctrl_uhi:clkctrl_cs_altclkctrl_uhi_component|clkctrl1" must be used  Error: Port(s) inclk[0] or inclk[1] of Clock Control Block "dso_pll:ll_inst|clkctrl_cs:clkctrl_cs6|clkctrl_cs_altclkctrl_uhi:clkctrl_cs_altclkctrl_uhi_component|clkctrl1" must be used  Error: Port(s) inclk[0] or inclk[1] of Clock Control Block "dso_pll:ll_inst|clkctrl_cs:clkctrl_cs7|clkctrl_cs_altclkctrl_uhi:clkctrl_cs_altclkctrl_uhi_component|clkctrl1" must be used  Error: Port(s) inclk[0] or inclk[1] of Clock Control Block "dso_pll:ll_inst|clkctrl_cs:clkctrl_cs8|clkctrl_cs_altclkctrl_uhi:clkctrl_cs_altclkctrl_uhi_component|clkctrl1" must be used  Error: Quartus II Partition Merge was unsuccessful. 8 errors, 0 warnings  Error: Peak virtual memory: 208 megabytes  Error: Processing ended: Wed Nov 02 17:43:24 2011  Error: Elapsed time: 00:00:06  Error: Total CPU time (on all processors): 00:00:04  Error: Quartus II Full Compilation was unsuccessful. 10 errors, 54 warnings  thank you very much

[Altera_Forum]

--- Quote Start ---  please paste the error here  --- Quote End ---   ？？？ can you tell me ? thank you very much ,i have pasted the error