Does Quartus Prime (I am using 21.1 Lite with an evaluation version of Active-HDL) support per-module simulation test benches? I have only been able to configure either RTL or gate-level simulation of the top level module thus far.
I have many years experience in XIlinx ISE and Vivado, and am accustomed to writing module:test bench pairs, and would really prefer this approach as I have some rather complex designs to port into new devices. Simulating only at the top level seems, well.... ridiculous.
Right-click at the submodules and select properties. Then, set the library path to the path where your project file located. So that those submodules can be compiled into Modelsim or Questa library and to be further used in testbench.
p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution and give Kudos.