Mux - Verilog code question

Altera_Forum · ‎03-18-2008

Hello everyone.

Mux verilog code below.

They do the same, but option 2 got huge delays and cannot meet timing. Conclusion: they have different fitter results but I thought they are the same?? or am I wrong??

I'm using quartus II 7.2, device cyclone II.

1.)

always @(*) begin

case (TxWrnum)

4'h0 : TXD_rdaddress <= TXD_rdaddressV[00*6+5:00*6+0];

4'h1 : TXD_rdaddress <= TXD_rdaddressV[01*6+5:01*6+0];

...........

4'hE : TXD_rdaddress <= TXD_rdaddressV[14*6+5:14*6+0];

4'hF : TXD_rdaddress <= TXD_rdaddressV[15*6+5:15*6+0];

default : TXD_rdaddress <= 16'h00;

endcase

end

2.)

assign TXD_rdaddress = TXD_rdaddressV[(TxWrnum*6)+:6];

thanks

Altera_Forum · ‎03-18-2008

In the second case, the compiler does not take into account, which array elements are actually accessed by the multiplexer, it may create multiplexer hardware for unused cases. What are the array bounds?

You may define the used cases explicitely by a function or a constant array instead of using a case construct:

for (I=0;I>=ARRAYSIZE;I=I+1)
  if (USED_ELEMENT(I) && I==TxWrnum)
    assign TXD_rdaddress = TXD_rdaddressV;

Altera_Forum · ‎03-19-2008

thanks fvm,

your code example is a nice idea and I guess what you say is correct.

I will try it later when I have time.

But I'm still wondering, In my code I'm using all cases, TxWrnum is 4 bits and all the 16 cases are defined, I think the problem is on the RHS that actually is much more complex than the example I gave.

I will check later.

thanks