NEED HELP! Verilog Digital Alarm Clock implementation on Altera DE2 Board

[Altera_Forum]

Hello Guys, I have been trying to implement a digital alarm clock using verilog, which can be turned off using a motion sensor and sends the sound output to a buzzer(its all implemented on the Altera DE2 board). I was able to make the clock work, and then I made the alarm part and it doesnt trigger the alarm. i assigned the alarm to an LED so if it gets triggered it should light up But for some reason my code broke. id appreciate some helpmodule inputmux(alarm_key_out, alarm_sw_out, clock_key_out, clock_sw_out, select, key_in, sw_in);

//Used to direct the control input to the alarm/clock

output reg alarm_key_out, alarm_sw_out, clock_key_out, clock_sw_out;

input select, key_in, sw_in;

always@(select)

case (select)

0: begin

clock_key_out = key_in;

clock_sw_out = sw_in;

end

1: begin

alarm_key_out = key_in;

alarm_sw_out = sw_in;

end

endcase

endmodule

module outputmux(hours_out, minutes_out, select, alarm_min_in, alarm_hours_in, clock_min_in, clock_hours_in);

parameter n = 8;

output reg [n-1 : 0] hours_out, minutes_out;

input [n-1: 0] alarm_min_in, alarm_hours_in, clock_min_in, clock_hours_in;

input select;

always @(select)

case (select)

0: begin

hours_out = clock_hours_in;

minutes_out = clock_min_in;

end

1: begin

hours_out = alarm_hours_in;

minutes_out = alarm_min_in;

end

endcase

endmodule

//Right now our counter only counts to 30 (or 12). If we change it to 60 then 1 minute == 2 minutes in real time.

//Check if the hour rolls over from at 30, I suspect that the clock hits 30, then has to hit 30 again. In which case it's a BCD error.

//Note: a roll over will *not* occur if the clock is in manual mode. 

module nBitCounter(count, reset_sig, CLK, manCLK, toggle);

parameter n = 8; // output size defualt 8 bit, must be able to store bitwise k value 

parameter k = 30; // ceiling

output reg [n-1:0] count;

output reg reset_sig; //Meant for a high output when count resets

input CLK, manCLK, toggle;

wire clockline;

assign clockline = toggle ? manCLK : CLK;

// Increment count on clock + also has seed value

always @(posedge clockline) //or posedge seed <- this breaks things

begin

if (count == k-1) begin

count = 0;

reset_sig = ~reset_sig;

end

else begin 

count = count + 1;

end

end

endmodule

module demuxer(a, s_in, x, y);

input a;

input s_in;

output reg x, y;

always @(a, s_in)

begin

case(s_in)

1: x = a;

0: y = a;

default: x = a;

endcase

end

endmodule

module sevenSegmentDisplay(ssOut, nIn);

output reg [0:6] ssOut;

input [3:0] nIn;

always @(nIn)

case (nIn)

4'b0000: ssOut = 7'b0000001;

4'b0001: ssOut = 7'b1001111;

4'b0010: ssOut = 7'b0010010;

4'b0011: ssOut = 7'b0000110;

4'b0100: ssOut = 7'b1001100;

4'b0101: ssOut = 7'b0100100;

4'b0110: ssOut = 7'b0100000;

4'b0111: ssOut = 7'b0001111;

4'b1000: ssOut = 7'b0000000;

4'b1001: ssOut = 7'b0001100;

endcase

endmodule

module binary_to_BCD(A,ONES,TENS,HUNDREDS);

input [7:0] A;

output [3:0] ONES, TENS;

output [1:0] HUNDREDS;

wire [3:0] c1,c2,c3,c4,c5,c6,c7;

wire [3:0] d1,d2,d3,d4,d5,d6,d7;

assign d1 = {1'b0,A[7:5]};

assign d2 = {c1[2:0],A[4]};

assign d3 = {c2[2:0],A[3]};

assign d4 = {c3[2:0],A[2]};

assign d5 = {c4[2:0],A[1]};

assign d6 = {1'b0,c1[3],c2[3],c3[3]};

assign d7 = {c6[2:0],c4[3]};

add3 m1(d1,c1);

add3 m2(d2,c2);

add3 m3(d3,c3);

add3 m4(d4,c4);

add3 m5(d5,c5);

add3 m6(d6,c6);

add3 m7(d7,c7);

assign ONES = {c5[2:0],A[0]};

assign TENS = {c7[2:0],c5[3]};

assign HUNDREDS = {c6[3],c7[3]};

endmodule

module add3(in,out);

input [3:0] in;

output [3:0] out;

reg [3:0] out;

always @ (in)

case (in)

4'b0000: out <= 4'b0000;

4'b0001: out <= 4'b0001;

4'b0010: out <= 4'b0010;

4'b0011: out <= 4'b0011;

4'b0100: out <= 4'b0100;

4'b0101: out <= 4'b1000;

4'b0110: out <= 4'b1001;

4'b0111: out <= 4'b1010;

4'b1000: out <= 4'b1011;

4'b1001: out <= 4'b1100;

default: out <= 4'b0000;

endcase

endmodule

module alarmstatecontroller(buzzerout, alarmtoggle, alarmstop, alarmstart, clk);

// This is the FSM. The buzzerout (currently represented by LEDG) does not actually 

// turn off. It may have to do with the switch in which case we can remove it. I don't think

// namespace is an issue but look into it. It might be worth while to assign LEDs to the states to see if

// they actually change. 

output reg buzzerout;

input alarmtoggle, alarmstop, alarmstart, clk;

wire trigger, dead;

assign trigger = alarmtoggle ? alarmstart : dead;

parameter n = 3;

parameter IDLE = 3'b001, RING = 3'b010;

reg [n - 1:0] STATE;

always @(trigger or alarmstop)

begin

case(STATE)

IDLE:

begin

buzzerout = 'b0;

if (trigger)

STATE = RING;

end

RING:

begin

if (alarmstop)

STATE = IDLE;

else begin

buzzerout = 1'b1;

end

end

default: STATE = IDLE;

endcase

end

endmodule

module alarmregister(alarmtrigger, clockhour, clockminute, alarmhour, alarmminute);

output reg alarmtrigger;

input [7:0]clockhour, clockminute, alarmminute, alarmhour;

always @(clockminute, clockhour, alarmminute, alarmhour)

begin

if (clockminute == alarmminute && clockhour == alarmhour) begin

alarmtrigger = 1'b1;

end else begin

alarmtrigger = 'b0;

end

end

endmodule

module clock(HEX3, HEX2, HEX1, HEX0, LEDR, LEDG, SW, KEY, CLOCK_50);

output [0:6]HEX3, HEX2, HEX1, HEX0;

output [1:0]LEDR, LEDG;

input [3:0] SW, KEY;

input CLOCK_50;

supply0 groundline;

wire mainclock, minuteclock, hourclock, inputtoclocksetsw, inputtoclocksetkey, clocksetminute, clocksethour;

wire alarmsetminute, alarmsethour, inputtoalarmsetkey, inputtoalarmsetsw, alarmtofsm;

wire [3:0] bcdminutesones, bcdminutestens, bcdhoursones,bcdhourstens;

wire [7:0]displayminutes, displayhours, clockminutesoutput, clockhoursoutput, alarmminutesout, alarmhoursout;

//Controls whats displayed on the HEX displays

inputmux ChangeInputController(inputtoalarmsetkey, inputtoalarmsetsw, inputtoclocksetkey, inputtoclocksetsw, SW[2], ~KEY[0], SW[0]);

outputmux ChangeOutputController(displayhours, displayminutes, SW[2], alarmminutesout, alarmhoursout, clockminutesoutput, clockhoursoutput);

demuxer ClockDeMux(inputtoclocksetkey, inputtoclocksetsw, clocksetminute, clocksethour);

demuxer AlarmDeMux(inputtoalarmsetkey, inputtoalarmsetsw, alarmsetminute, alarmsethour);

//Display Control

binary_to_BCD Minutes(displayminutes,bcdminutesones,bcdminuteste ns,HUNDREDS);

binary_to_BCD Hours(displayhours,bcdhoursones,bcdhourstens,HUNDR EDS);

sevenSegmentDisplay HexDisplayMinutesZero(HEX0, bcdminutesones);

sevenSegmentDisplay HexDisplayMinutesOne(HEX1, bcdminutestens);

sevenSegmentDisplay HexDisplayHoursZero(HEX2, bcdhoursones);

sevenSegmentDisplay HexDisplayHoursOne(HEX3, bcdhourstens);

//Create seconds tick

nBitCounter ClockDelay(count, mainclock, CLOCK_50, seed, toggle);

defparam ClockDelay.n = 25;

defparam ClockDelay.k = 25000000;

assign LEDR[0] = mainclock;

//Count Seconds

nBitCounter SecondsTick(count, minuteclock, mainclock, seed, SW[1]);

//Count Minutes

nBitCounter MinutesTick(clockminutesoutput, hourclock, minuteclock, clocksetminute, SW[1]);

//Count Hours

nBitCounter HoursTick(clockhoursoutput, reset_sig, hourclock, clocksethour, SW[1]);

defparam HoursTick.k = 12;

//Alarm Minutes

nBitCounter AlarmMinuteCounter(alarmminutesout, reset_sig, CLK, alarmsetminute, SW[1]);

//Alarm Hours

nBitCounter AlarmHourCounter(alarmhoursout, reset_sig, CLK, alarmsethour, SW[1]);

defparam AlarmHourCounter.k = 12;

//Alarm Triggering

alarmregister AlarmRegisterComp(alarmtofsm, clockhoursoutput, clockminutesoutput, alarmhoursout, alarmminutesout);

assign LEDR[1] = alarmtofsm;

//When the FSM is enabled the LED (means alarm is triggered) does not light up.

//alarmstatecontroller AlarmSoundControl(LEDG[0], SW[3], ~KEY[2], alarmtrigger, mainclock);

endmodule