Showing results for 
Search instead for 
Did you mean: 
Valued Contributor III

Names not found by TimeQuest

My Cyclone V SOC project produced output works correctly under normal conditions. The QSYS configured HPS system contains among others an Ethernet switch IP (qxp file, sdc file and VHDL wrapper for the port signals), which is for me a black box.  


But the Fitter process generates a lot of warnings which are related to constraints in different sdc files, among them auto generated constraint files from QSYS and also the Ethernet switch constraint file. Examples: 

Warning (332174): Ignored filter at hps_sdram_p0.sdc(303): memory_mem_ck could not be matched with a clock 

Warning (332174): Ignored filter at xxx_hpc_hps_0_hps_io_border.sdc(53): hps_io_hps_io_uart0_inst_TX could not be matched with a port 


The self-written sdc file which constrains the clock signals in the top level makes no problems. 


The signal names from the warnings can be found in the source files (except the black box internal signals). But with the name finder tool of TimeQuest I can find the signal names of the constraints which are accepted by the fitter and I cannot find the names which I see in the warnings. Very strange for instance is that in the QSYS generated "xxx_hpc_hps_0_fpga_interfaces.sdc" file only one of the four constraints is not accepted and only the related signal cannot be found with Name Finder. But the QSYS generates source file contains all the signal names. 


I am using Quartus 14.0. 


Is there any idea what I can do? The constraints, especially for the embedded switch, will be neccessary for a reliable function under all conditions. 

Best regards
0 Kudos
2 Replies
Valued Contributor III

It sounds to me as if those sdc files are simply out of date. Delete, regenerate and try them again. 



0 Kudos
Valued Contributor III

Hi Alex, thanks for your response. 


The sdc files are freshly generated by QSYS. But meanwhile I found out, that the problem seems to come with the synthesis process. I followed the ways of two signals through the modules. The timing netlist is based on the synthesis result, and the synthesis may remove or replace some signal names for different reasons. 


One interface signal from the HPS is simply not used. It's routed by QSYS to the top level and there it is open. I think, that the synthesis process removes the signal completely and so it's not to be found by TimeQuest. But QSYS still generates a constraint with this signal name... 


The other HPS interface signal is connected to an I/O pin in the top level module and there it gets the name which I assigned to the I/O pin. When I replace the original name in the QSYS generated constraint by my I/O pin name, it works! I think, that the synthesis replaces the original signal name with my I/O name. With the TimeQuest Name Finder I can find my I/O name, but not the original name from QSYS. 


Of course, now I could replace all the concerning signal names in the constraint files by their replacements. But that's a bad solution. Always when the system is newly generated by QSYS I have to patch the files by my own. Or I store my own sdc files in another place and change the project settings for the sdc file path. But then, always when the HSP system configuration was changed, I carefully have to check, if there something has changed in the constraints. 


Has someone an idea for a better solution? 


Best regards, 

0 Kudos