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Hi,
RTL-Simulation with Questa Intel Starter FPGA Edition using Nativelink fails under following conditions:
- there are two variations of the GPIO Lite Intel FPGA IP core included;
- any task other than "Analysis & Synthesis" has been run before starting "RTL Simulation".
Questa will look for vho file which has not been generated for the ip.
Find attached Quartus archive gpio_demo.qar targetting MAX 10 device with instances of PLL IP and GPIO Lite IP.
Steps to simulate successfully:
- Open gpio_demo.qar in Quartus Prime 22.1 Lite Edition.
- Run Analysis & Synthesis.
- Start RTL-Simulation: Questa Intel Starter FPGA Edition 2021.2 runs successfully.
Steps to reproduce simulation error:
- Run Fitter (Place & Route) or Compile Design.
- Start RTL-Simulation: Questa fails with message:
# vcom -93 -work work {O:/work/intel/gpio_demo/ip/oddr/oddr.vho}
# Questa Intel Starter FPGA Edition-64 vcom 2021.2 Compiler 2021.04 Apr 14 2021
# Start time: 13:07:32 on Apr 15,2024
# vcom -reportprogress 300 -93 -work work O:/work/intel/gpio_demo/ip/oddr/oddr.vho
# ** Error: (vcom-7) Failed to open design unit file "O:/work/intel/gpio_demo/ip/oddr/oddr.vho" in read mode.
# No such file or directory. (errno = ENOENT)
Further investiagtions show that:
- the content of file gpio_demo_run_msim_rtl_vhdl.do in in sub-folder simulation/questa changes depending on the task running before RTL Simulation has been started;
- Quartus Prime 23.1 Lite Edition shows same behaviour;
- project with only one variation of GPIO Lite IP does not show this behaviour
(see attached Quartus archive gpio_demo_oddr_only.qar).
So it seems to be an issue of the script generation within NativeLink.
Is this the intended behaviour?
I expect that RTL simulation runs successfully disregarding which task has been run before.
Best regards,
Uwe
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It might be a potential bug and I will confirm this with the engineering.
1) Run Analysis & Synthesis ->RTL simulation Passed.
2) Run Analysis & Synthesis, Then Run Fitter -> RTL simulation Error.
3) Run Fitter directly -> RTL simulation Passed.
Case (3) is particularly interesting as it works after fitter stage. I recommend avoiding situation (2) as a workaround.
FYI, in cases where this error arises in Quartus Standard, we can only provide a workaround unless there's no available solution.
Thank you for your understanding.
Regards,
Richard Tan
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I have not receive any update from the engineering team.
I will continue to follow up with the engineering team and provide you with an update as soon as possible.
Thank you for your patience and understanding.
p/s: Please keep in mind that any work involving our engineering team may take some time, ranging from a few days to a few weeks, depending on the complexity of the issue.
Regards,
Richard Tan
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Unfortunately, as a workaround is available (running with only Analysis and Synthesis), there are no plans to fix this issue in the Quartus Standard software. I apologize for any inconvenience caused, as support is limited for the Quartus Standard edition.
Thank you for your understanding.
With that, I will transition this thread to community support. If you have any further questions or concerns, please don't hesitate to reach out.
Thank you and have a great day!
Regards,
Richard Tan
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Hi Richard,
thank you for your support.
Do you have any further information when this bug will be triggered, for instance:
Is it only related to the GPIO Lite IP?
Is it only related to a certain type of IP?
Is it related to the number of instances of an IP?
Is it related to the number of variations of an IP?
Regards,
Uwe
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