Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
15543 Discussions

Need help designing a Custom IP with Avalon Slave Interface

Altera_Forum
Honored Contributor II
1,319 Views

Hello all. 

 

I need help on designing a Custom IP (for use on Qsys) in verilog, which has a Avalon Slave Interface connected to Avalon Master of Nios II Processor. And I want to transfer data into the module's register through de-referencing. Problem is that I'm fairly new to this Avalon Interface stuff, and I don't understand how Nios2 Processor accesses the custom IP through Avalon Interface, and the data is input. 

 

I want to input data into the module by using pointers in c code, like : 

| volatile int * addr = (int *) (base_addr_of_custom_ip); 

| addr = 0x00000001; 

 

 

The custom module's verilog code tries to store the input data like this : 

| input [4:0] s_addr; 

| input [31:0] s_wdata; //Avalon Interface write data 

| reg [31:0] data; 

| always @(posedge clk) begin 

| data <= s_wdata; 

| end 

 

(note that this is not a complete slave interface design : I need only one set of data input for now) 

 

 

That's about it. So the question is : How does writing into module work, when by de-referencing in c code? 

 

 

 

EDIT : Okay I somehow made double post and it's all messed up. This one isn't supposed to be uploaded...
0 Kudos
2 Replies
Altera_Forum
Honored Contributor II
146 Views

Woah what? Somehow I made double post, and both of their contents are invisible to me... 

What's going on... 

 

+) I'll contact the Admins to have the two threads removed. Sorry.
Altera_Forum
Honored Contributor II
146 Views

When you add the custom component to your Qsys (now called Platform Designer) system, you set a base address for it in the master's address space. When you generate the system, you get a .sopcinfo file that is then used by the Nios II EDS (Eclipse) to create header files with macros for accessing the slave at the appropriate address. 

 

Note: you need a write enable signal in your Verilog code.
Reply