Need help for constraining 12-bit serial ADC

[Altera_Forum]

I'm using an ADC12DS080, a 80MHz 12-bit serial ADC. It has 2 channels per an input so that every edge of the frame clock I get a new sample. I use the data_clk as the DDR input clock and I believe I have that constrained correctly according to the guides. However, I can't seem to get the frame_clk's relationship with the data_clk correct. It keeps coming out as .001. when it should be around 1.042 ns. The data_clk is 240 MHz and the frame_clk is 40MHz. I shift the frame_clk by 2.081 ns to get the frame_clk in sync with delay from the DDIO_INPUT megafunction. I then also generate a 80MHz clock with the same delay.  

 Listed below are my constraints:  create_clock -name fpga_clk_frame -period 25 # # VIRTUAL CLOCK DATA# # create_clock -name ext_clk1 -period 4.167# # INPUT CLOCK WITH 90 DEGREES PHASE SHIFT create_clock -name fpga_clk_data -period 4.167 -waveform {1.042 3.125} # ##################3 FAST ADC# ####################################3 set_input_delay -clock ext_clk1 -max 0.250 }] set_input_delay -clock ext_clk1 -min -0.250 }] set_input_delay -clock ext_clk1 -max 0.250 }] -clock_fall -add_delay set_input_delay -clock ext_clk1 -min -0.250 }] -clock_fall -add_delay set_input_delay -clock ext_clk1 -max 0.250 }] set_input_delay -clock ext_clk1 -min -0.250 }] set_input_delay -clock ext_clk1 -max 0.250 }] -clock_fall -add_delay set_input_delay -clock ext_clk1 -min -0.250 }] -clock_fall -add_delay set_false_path -setup -rise_from -fall_to set_false_path -setup -fall_from -rise_to set_false_path -hold -rise_from -rise_to set_false_path -hold -fall_from -fall_to set_false_path -setup -rise_from -rise_to set_false_path -hold -rise_from -rise_to

[Altera_Forum]

The 4.167 won't line up with 25ns, it lines up with 25.002ns. So they're not considered to be related. Make the other clocks 4.166 and FRCLK 24.996. (I figure it's better to make them tighter instead of leaving the other clock at 4.167 and loosening the FRCLK to 25.002ns.

[Altera_Forum]

I would of never though of that. Thanks for the help. Timequest now gives a proper relationship of 1.041ns.

[Altera_Forum]

There's a TQ user guide I put together on www.alterawiki.com(just click on Populer Pages and it's about the 10th one down). I think the second chapter is on clock relationships, and might help show why this occurs. Right now you've described two clocks with period that never line up. I know it seems like they're "close enough", but TimeQuest never does that for independent clocks.  

Another option would be to make one a generated clock. You'd get a warning that it can't find a connection from the master, which is fine. THe benefit of a generated clock is that you can do -divide_by 6 or something like that, and it then knows that even if it rounds to 3 digits and they no longer line up, that it's still a 6x multiple on period. But I think what you currently have is the most straightforward.

[Altera_Forum]

Between your guide and the on-line training I was able to get as far as I did I just never realized that this was the issue. Of course now my PLL is complaining that its input isn't 40MHz.

[Altera_Forum]

If fractions is the issue then use frequency directly: 

 create_clock -period "40 MHz" [get_ports ...]