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Need help in verilog file creation

Altera_Forum
Honored Contributor II
‎10-28-2015 04:50 AM
2,579 Views

I have a file which is extended to .tdf (Text Design File) from altera library. I want to convert it to traditional verilog code. 

Can anyone help in this regard? 

thanks, 

mahee
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Altera_Forum
Honored Contributor II
‎10-28-2015 06:52 AM
1,860 Views

If you download Xilinx ISE tools, it has a program called XPORT that allows you to convert AHDL files (.tdf) to VHDL or Verilog. Otherwsie you'll have to do it manuallly

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