Negative Set Up time in Timing report

[Altera_Forum]

Hi all,  

My "micro setup delay" is negative (-0.04). Why is it? Thanks a lot. Below is part of Classical Timing Report. It's true that fmax = 1/(tco + reg-to-reg-delay + tsu). tsu in the below report is negative. That's weird!!!  Thanks, guys. Jeff  =================================================== Info: Slack time is -4.487 ns for clock "clk" between source register "int_input2[3]" and destination register "output[0]~reg0"  Info: Fmax is 182.25 MHz (period= 5.487 ns)  Info: + Largest register to register requirement is 0.736 ns  Info: + Setup relationship between source and destination is 1.000 ns  Info: + Latch edge is 1.000 ns  Info: Clock period of Destination clock "clk" is 1.000 ns with offset of 0.000 ns and duty cycle of 50  Info: Multicycle Setup factor for Destination register is 1  Info: - Launch edge is 0.000 ns  Info: Clock period of Source clock "clk" is 1.000 ns with offset of 0.000 ns and duty cycle of 50  Info: Multicycle Setup factor for Source register is 1  Info: + Largest clock skew is 0.000 ns  Info: + Shortest clock path from clock "clk" to destination register is 3.367 ns  Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_T2; Fanout = 1; CLK Node = 'clk'  Info: 2: + IC(0.135 ns) + CELL(0.000 ns) = 1.235 ns; Loc. = CLKCTRL_G3; Fanout = 35; COMB Node = 'clk~clkctrl'  Info: 3: + IC(1.466 ns) + CELL(0.666 ns) = 3.367 ns; Loc. = LCFF_X66_Y48_N13; Fanout = 1; REG Node = 'output[0]~reg0'  Info: Total cell delay = 1.766 ns ( 52.45 % )  Info: Total interconnect delay = 1.601 ns ( 47.55 % )  Info: - Longest clock path from clock "clk" to source register is 3.367 ns  Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_T2; Fanout = 1; CLK Node = 'clk'  Info: 2: + IC(0.135 ns) + CELL(0.000 ns) = 1.235 ns; Loc. = CLKCTRL_G3; Fanout = 35; COMB Node = 'clk~clkctrl'  Info: 3: + IC(1.466 ns) + CELL(0.666 ns) = 3.367 ns; Loc. = LCFF_X66_Y48_N11; Fanout = 3; REG Node = 'int_input2[3]'  Info: Total cell delay = 1.766 ns ( 52.45 % )  Info: Total interconnect delay = 1.601 ns ( 47.55 % )  Info: - Micro clock to output delay of source is 0.304 ns  Info: - Micro setup delay of destination is -0.040 ns  Info: - Longest register to register delay is 5.223 ns  Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X66_Y48_N11; Fanout = 3; REG Node = 'int_input2[3]'  Info: 2: + IC(1.128 ns) + CELL(0.596 ns) = 1.724 ns; Loc. = LCCOMB_X65_Y48_N6; Fanout = 1; COMB Node = 'Comparator_16bit:UT|LessThan1~215'  Info: 3: + IC(0.000 ns) + CELL(0.086 ns) = 1.810 ns; Loc. = LCCOMB_X65_Y48_N8; Fanout = 1; COMB Node = 'Comparator_16bit:UT|LessThan1~217'  Info: 4: + IC(0.000 ns) + CELL(0.086 ns) = 1.896 ns; Loc. = LCCOMB_X65_Y48_N10; Fanout = 1; COMB Node = 'Comparator_16bit:UT|LessThan1~219'  Info: 5: + IC(0.000 ns) + CELL(0.086 ns) = 1.982 ns; Loc. = LCCOMB_X65_Y48_N12; Fanout = 1; COMB Node = 'Comparator_16bit:UT|LessThan1~221'  Info: 6: + IC(0.000 ns) + CELL(0.190 ns) = 2.172 ns; Loc. = LCCOMB_X65_Y48_N14; Fanout = 1; COMB Node = 'Comparator_16bit:UT|LessThan1~223'  Info: 7: + IC(0.000 ns) + CELL(0.086 ns) = 2.258 ns; Loc. = LCCOMB_X65_Y48_N16; Fanout = 1; COMB Node = 'Comparator_16bit:UT|LessThan1~225'  Info: 8: + IC(0.000 ns) + CELL(0.086 ns) = 2.344 ns; Loc. = LCCOMB_X65_Y48_N18; Fanout = 1; COMB Node = 'Comparator_16bit:UT|LessThan1~227'  Info: 9: + IC(0.000 ns) + CELL(0.086 ns) = 2.430 ns; Loc. = LCCOMB_X65_Y48_N20; Fanout = 1; COMB Node = 'Comparator_16bit:UT|LessThan1~229'  Info: 10: + IC(0.000 ns) + CELL(0.086 ns) = 2.516 ns; Loc. = LCCOMB_X65_Y48_N22; Fanout = 1; COMB Node = 'Comparator_16bit:UT|LessThan1~231'  Info: 11: + IC(0.000 ns) + CELL(0.086 ns) = 2.602 ns; Loc. = LCCOMB_X65_Y48_N24; Fanout = 1; COMB Node = 'Comparator_16bit:UT|LessThan1~233'  Info: 12: + IC(0.000 ns) + CELL(0.086 ns) = 2.688 ns; Loc. = LCCOMB_X65_Y48_N26; Fanout = 1; COMB Node = 'Comparator_16bit:UT|LessThan1~235'  Info: 13: + IC(0.000 ns) + CELL(0.086 ns) = 2.774 ns; Loc. = LCCOMB_X65_Y48_N28; Fanout = 1; COMB Node = 'Comparator_16bit:UT|LessThan1~237'  Info: 14: + IC(0.000 ns) + CELL(0.506 ns) = 3.280 ns; Loc. = LCCOMB_X65_Y48_N30; Fanout = 1; COMB Node = 'Comparator_16bit:UT|LessThan1~238'  Info: 15: + IC(0.611 ns) + CELL(0.651 ns) = 4.542 ns; Loc. = LCCOMB_X66_Y48_N18; Fanout = 1; COMB Node = 'Comparator_16bit:UT|Mux0~66'  Info: 16: + IC(0.367 ns) + CELL(0.206 ns) = 5.115 ns; Loc. = LCCOMB_X66_Y48_N12; Fanout = 1; COMB Node = 'Comparator_16bit:UT|Mux0~67'  Info: 17: + IC(0.000 ns) + CELL(0.108 ns) = 5.223 ns; Loc. = LCFF_X66_Y48_N13; Fanout = 1; REG Node = 'output[0]~reg0'  Info: Total cell delay = 3.117 ns ( 59.68 % )  Info: Total interconnect delay = 2.106 ns ( 40.32 % ) Warning: Can't achieve timing requirement Clock Setup: 'clk' along 34 path(s). See Report window for details.

[Altera_Forum]

I would be surprised if anyone knew exactly(the exact timing models are probably known by internal hardware engineers at Altera.) That being said, I've seen timing numbers represent more than their name. The timing reports very nicely count routing, cell, register delays, but in the silicon it's often not that precise. Tsu is a very idealized term, but it's also racing against the clock, so it might be that the relationship of where the "clock" starts and the "data" starts is throwing it off. If you can get the micro Th of the same path, perhaps it seems out of whack too, but enough that the combination makes sense. 

(In the end, I'm not sure and you should probably file an SR if you need an exact reason, but if I were to wager, I'd bet the full analysis is correct, even if the micro-parameter looks off.)

[Altera_Forum]

THanks :) ... Happy holidays !

[Altera_Forum]

The person who started the http://www.alteraforum.com/forum/showthread.php?t=1745 thread also had a negative micro tsu.

[Altera_Forum]

It is perfectly ok for a uTsu to be negative. The reason has to do with Software modeling: 

 - The boundary of the software model may not be exactly the same as the register in the HW. For modeling reasons, Quartus developers can move the 'data' and/or 'clk' pins to match the software representation. There can be additional delay between the point Quartus considers the 'clk' pin or the register, and the actual HW register itself. The model is still 100% accurate and the difference is all about considering 10ps as routiing delay on the clk pin, or part of register uTsu (numbers are just examples). At the end, the uTsu is basically:  uTsu = delay from model's data pin to ideal register  - delay from model's clk pin to ideal register  + ideal uTsu   - In order for Altera to ensure that TimeQuest or Classic report the worst case slack, Quartus develops sometimes need to add additional guard bands. This guard bands can some times show in funny ways. This is more so in Classic where Rise/Fall differences are not modeled.  So, don't worry too much about the uTsu and just look at your path's total slack. It will be correct.