New to Quartus, VHDL to Gates?

[Altera_Forum]

Alright, so I just downloaded Quartus II Net, and created a really simple VHDL file for a carrly lookahead adder. Is there any way to show the actual gate level schematic for it? Also, I'd like to do simple simulation, but I have no idea where to even start with that, or how to do it. All I want to do is be able to supply numbers and see how the gate level system actual works for various thing. 

 Also, I'm trying to design these things to be clockless, so I don't need to generate clocks or anything for their simulation.  What I'm actually trying to do is design stuff that I can use to make a custom ALU in Minecraft ( en.wikipedia.org/wiki/Minecraft ) using their "Redstone" circuit system (which is entirely composed of using NOTs to create gates).  I want it to be clockless because redstone is quite slow without having a clock slow it down further.

[Altera_Forum]

For your first question: when you have compiled some code go to the RTL viewer: Tools -> netlist viewers -> RTL View. That will show you all the gates in the design. But remember that this will have all boolean algebra reduced to minimal design, following the rules of things like  

 A and A = A A and !A =0 A or !A = 1  etc  What you want to use is Modelsim. With this you can simulate anything. You can simulate code directly, and manipulate it from the code. you could write some code like this in VHDL and simulate it and watch the waveform in modesim:   signal a,b,c,d : std_logic; begin a <= '0', '1' after 10 ns, '0' after 30 ns; b <= '1', '0' after 40 ns; c <= a and b; d <= a nand b; end architecture;   Now you wont be able to compile this in quartus, but at least you can simulate it.

[Altera_Forum]

An in response to your "Redstone" logic - your ALU is going to get very complicated, very quickly. Im guessing the clock slows it down because you're actually adding the clocking circuit into the logic. The thing about clocks is it allows for the development of a pipeline. In the real world, there are actual time delays for a signal to pass through logic. Without a clock, it would be a very slow processor. The clock may increase the latency through the design, but you can push much much more data through it.  

 As Im guessing there is no actual delay through this redstone system, then asynchronous design is possible.  I wouldnt try and run much on an FPGA without a clock.

[Altera_Forum]

Well, like I said I'm rather new to this stuff. I've got a decent foundation in digital logic (enough to understand boolean algebra, flip flops, etc.), but I'm still really new to any of the design aspects. I took 1 digital circuits class because my program in college included it, but we only got about as far as discussing flip flops, really. Nothing about design. 

 Is there a way to make the RTL viewer show each individual pin, rather than show them 2 inputs as a collection of wires? if I'm going to design something in VHDL and implement it in Redstone, I'd like to have a schematic I can follow without having to mentally separate the lines...  But yeah, I was more or less waiting for someone to tell me why the idea of not using a clock was a bad one, lol.  I'm not sure if there is a delay through the "wire" itself in the Redstone system, but I know that every primitive inverter that you use adds a delay, so I may have to try to optimize for the minimal amount of inverters used.  Also, while I'm discussing this, does anyone know a good resource to describe how to implement multiplication and division in an ALU? I had a hell of a time finding a decent resource that explained CLAs in a way that I could actually understand (since I don't have a very strong academic background in digital systems). And is there anywhere that explains Brent-Kung adders, Kogge-Stone adders in a simpler way? I'd ideally like to implement one of those, rather than a CLA, but it took me a while to figure out how a CLA really worked (I could have coded one in VHDL easily enough without understanding it, but I absolutely hate doing stuff when I don't actually understand what's happening).  I would have liked to post a link to a video on youtube that someone made, because they've already created a 16-bit ALU minecraft. But since this forums has that "no links till you've posted 5 times" thing, I couldn't. He used ripple carry adders for his ALU though, and I know that the adders are one of the most important parts of the ALU.

[Altera_Forum]

I dont understand the problem with the RTL viewer. if you have in and out ports on the entity, they will be pins, with the internal logic connecting them together. 

 The basic principle to multplication is addition. you need for an n bit number, you need n-1 adders. the idea is you are summing a load of bit-shifted values.  for 7 (111) x 5 (101) = 35:   1 1 1 (7) x 1 0 1 (5) ----------------- 1 1 1 0 0 x4 + 0 0 0 0 0 x2 (0 in this case + 0 0 1 1 1 ------------------ 1 0 0 0 1 1 = 32 + 2 + 1   As for division, dont even think about it. The best way to do A/B is to actually do A X 1/B where 1/B is pre calculted in fixed point. Division circuits are huge and generally best avoided. Most FPGAs now have embedded multipliers hence why the Ax 1/B calculation is much easier.

[Altera_Forum]

I've gotta say thanks for all the quick replies. Most FPGA related forums I've seen online seem to be pretty much dead :/ 

 I think I'll be able to get a multiplication circuit set up now.  The RTL viewer issue was that it automatically had all the inputs grouped. All I had to do was right click one of the pins and click "Ungroup selected nodes".

[Altera_Forum]

The number of bits in each Carry/Propagate group is a function of how many inputs the and/or blocks can have and the width of the operands. However in this case, it may be unlimited. Then it looks like the other adders use trees that or the operands, then if a carry is generated in the least significant bit and all other positions or'd are 1there will be a carry out of the most significant. Then if the any position generates a carry and all the bits or'd to any higher position the carry is propagated to that position. Consider 32 bit operands. One carry condition would need 30 inputs to or the propagates between the most and least significant, the and that with the least significant carry, then a 30 input or to or all of the remaining positions(30?), then 29, 28 ... and so on. 

 Binary integer multiply is a series of add and shifts. If the LSB of the multiplier is 1, add the multiplicand to the product, if 0, do not add, shift the product and multiplier right 1 position, discarding LSB of the multiplier, repeat for the width of the multiplier to produce the product width equal to the sum of m'plier and m'cand widths.  Division essentially does the reverse, but first complement opnds to make both positive and remember if one was negative and the other positive. Trial subtract the divisor from the high half of the double wide dividend, if negative just shift otherwise add 1 to the quotient, shift quotient and dividend 1 position left, repeat for the width of the divisor. What is left of the dividend is the remainder. Also if the signs were different complement the quotient because the algorithm uses positive operands but the result has to be negative. I may have forgotten some detail, but if you try a case or two with small numbers the basic notion should come thru.