[bug report QII 9.1] verilog HDL design entity loose capital latters from name

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[bug report QII 9.1] verilog HDL design entity loose capital latters from name

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Hi, i dont know where to post a bug reports, therefore i try to post it here.

i use QII 9.1 for winXP.

When Create verilog HDL design file from current file - generated an entity with its name of all lower characters, besides an capital letters of original blocks cheme. But higher-level schemes that contain this block use exact name to instantiate it.

Therefore when try to simulate scheme in modelsim i got an error cause it cant load used entities cause of their name lowered vs exact used.

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