Newbie Question

[Altera_Forum]

Hi guys. I am new at VHDL and Quartus II software so this might be a really stupid or trivial question but I can't seem to figure out why the following code is giving a syntax error "near text "PROCESS": expecting 'if' (And several other 'expecting' something errors near words BEGIN, PROCESS etc.) Thanks in advance. 

 library ieee; use ieee.STD_LOGIC_1164.ALL; use ieee.STD_LOGIC_ARITH.ALL; use ieee.STD_LOGIC_UNSIGNED.ALL;   entity test2 is  Port ( x1 : in STD_LOGIC;  x2 : in STD_LOGIC;  clock : in STD_LOGIC;  candy : out STD_LOGIC;  cent5_eject : out STD_LOGIC;  cent10_eject : out STD_LOGIC;  cent25_eject : out STD_LOGIC); end test2;  architecture Behavioral of test2 is  VARIABLE temp_count, tot_count, out_check, double_o : INTEGER := 0;  SIGNAL double_out : STD_LOGIC := '0';  BEGIN  -- Output Logic process  output_logic : PROCESS (x1, x2, clock)  BEGIN  IF clock'event AND clock = '1' THEN  IF (x1 = '0' AND x2 = '1') THEN  temp_count := 5;  ELSE IF (x1 = '1' AND x2 = '0') THEN  temp_count := 10;  ELSE IF (x1 = '1' AND x2 = '1') THEN  temp_count := 15;  ELSE  temp_count := 0;  END IF;  END IF;  END PROCESS output_logic; -- The line with the error  -- CLOCK Configuration Process  clock_config : PROCESS (clock) BEGIN   IF clock'EVENT AND clock = '1' AND double_out = '0' THEN  tot_count := tot_count + temp_count;  ELSE IF clock'EVENT AND clock = '1' AND double_out = '1' THEN -- Another Error here (Expecting a sequential statement or a "(")  CASE double_o IS  WHEN 10 =>  cent5_eject <= '0'; cent10_eject <= '1'; cent25_eject <= '0'; candy <= '0'; double_out <= '0'; double_o := 0;  WHEN 5 =>  cent5_eject <= '1'; cent10_eject <= '0'; cent25_eject <= '0'; candy <= '0'; double_out <= '0'; double_o := 0;  WHEN OTHERS =>  END CASE;  END IF; END PROCESS clock_config;   outs_confirm : PROCESS (tot_count) BEGIN  IF tot_count = 65 THEN  tot_count := 0;  cent5_eject <= '0'; cent10_eject <= '0'; cent25_eject <= '0'; candy <= '1';  ELSE IF tot_count > 65 THEN  out_check := tot_count - 65;  tot_count := 0;  IF out_check >= 25 THEN  cent5_eject <= '0'; cent10_eject <= '0'; cent25_eject <= '1'; candy <= '1';  ELSE IF out_check >= 10 THEN  CASE out_check IS  WHEN 10 =>  cent5_eject <= '0'; cent10_eject <= '1'; cent25_eject <= '0'; candy <= '1';  WHEN 15 =>  cent5_eject <= '1'; cent10_eject <= '1'; cent25_eject <= '0'; candy <= '1';  WHEN 20 =>  cent5_eject <= '0'; cent10_eject <= '1'; cent25_eject <= '0'; candy <= '1'; double_out <= '1'; double_o = 10;  END CASE;  ELSE IF out_check >= 5 THEN  cent5_eject <= '1'; cent10_eject <= '0'; cent25_eject <= '0'; candy <= '1';  END IF;  END IF; END PROCESS outs_confirm;  END Behavioral;

[Altera_Forum]

The compiler is complaining about missing end if statements. That's because the correct syntax is 

IF <cond1> THEN <block1> ELSIF <cond2> THEN <block2> ELSE <block3> END IF;  Quartus has nice VHDL templates accessible in the editor, they can help you in case of VHDL syntax doubts.