No Output from VHDL code !?

[Altera_Forum]

Hello all,  

 Being a newbie in VHDL, I am sure theres a stupid mistake somewhere. I just can not get my head around it.   There is no output for 'F1' and 'deltaF' below. I am using @ltera qu(at)rtus as the compiling tool and it gives no error during compilation and simulation.   Can someone please help.    ibrary IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; entity computation2 is port ( Clock: in STD_LOGIC; reset: in STD_LOGIC; Digit: in STD_LOGIC_VECTOR (23 downto 0); DigitValid: in STD_LOGIC; F1: out STD_LOGIC_VECTOR (27 downto 0); deltaF: out STD_LOGIC_VECTOR(27 downto 0) ); end computation2; architecture computation2 of computation2 is signal I_WordNumber:INTEGER; signal I_FC:INTEGER; signal I_BW:INTEGER; signal I_BW1:INTEGER; signal I_WRF:INTEGER; signal I_F1:INTEGER; signal I_DF:INTEGER; begin process (Clock,DigitValid,reset) begin if (reset='1') then I_WordNumber <=1; I_BW <=1; I_WRF <= 1; I_FC<=1; I_DF<=0; elsif (DigitValid'Event and DigitValid='0') then if(I_WordNumber=1) then I_BW <= CONV_INTEGER(Digit); I_WordNumber<=2; elsif(I_WordNumber=2) then I_BW <= I_BW*1000; I_FC <= CONV_INTEGER(Digit); I_WordNumber<=3; elsif (I_WordNumber=3) then I_FC <= I_FC*1000; I_WRF<=CONV_INTEGER(Digit); I_WordNumber<=4; elsif (I_WordNumber=4) then I_WordNumber<=1; I_F1 <= I_FC - (I_BW/2); I_DF <= (I_BW * I_WRF * 114) / 300000000000; end if; F1 <= CONV_STD_LOGIC_VECTOR (I_F1, 28); deltaF <= CONV_STD_LOGIC_VECTOR (I_DF, 28); end if; end process; end computation2;

[Altera_Forum]

As being said in another discussion, the / 300000000000 must be expected constant zero cause it overflows integer range.

[Altera_Forum]

Since you're a newbie I give you some suggestions. 

First of all NEVER use in VHDL signal such as integers, but use always standard_logic_vector. Moreover in a sequential process try to use only the Reset and the Clock in the sensitivity list. All other signals must be clocked (pay attention that they're correctedly clocked among different clock domains).  In your code here you've specified also a clock in the sensitivity list but never used it in the code, remove it from the sensitivity list of the process.  Remember that a "*" is an hardware multiplication, so pay attention to timings. It'll be better if you not use the "*" but that you define the hardware multiplicator and then specify its input and output taking into accout the latency it haves (ofc use a clocked one version).  Hope that it could be of use for your future.  Best regards

[Altera_Forum]

Hello, 

 must comment two things!    --- Quote Start ---  In your code here you've specified also a clock in the sensitivity list but never used it in the code, remove it from the sensitivity list of the process.  --- Quote End ---    Apart from confusing the author himself and project coworkers, which effect would you expect particularly from superfluous sensitivity list members. I assume - none.    --- Quote Start ---  It'll be better if you not use the "*" but that you define the hardware multiplicator.  --- Quote End ---    Which purpose does it serve, except from making the code less readable?  I regard it a valuable feature of HDL compilers, that they are able to infer certain structures, including multipliers and memory from HDL code and generally try to utilize it for compact, functional code.  In the "no-output" example, you can doubt if multiplications and other long-winded operations are needed at all, but that's a different question.  Regards, Frank

[Altera_Forum]

I've given him some suggestion cause he stated that is a newbie and a good starting in this world is very important in my opinion. 

It must be clear that VHDL/Verilog is a different thing of all other programmer languages. Here you're describing what will be physicallly inferred. Stated this I try to answer about my suggestions.    --- Quote Start ---   Apart from confusing the author himself and project coworkers, which effect would you expect particularly from superfluous sensitivity list members. I assume - none.   --- Quote End ---    Code styling is not superfluous and moreover some "stupid" compilers will do a check for each signal in the sensitivity list and route the not used signal to the block also if not used. Apart that no issue (but in a congestionated design the route of useless signals must be prevent.    --- Quote Start ---   Which purpose does it serve, except from making the code less readable?  I regard it a valuable feature of HDL compilers, that they are able to infer certain structures, including multipliers and memory from HDL code and generally try to utilize it for compact, functional code.   --- Quote End ---    The code will maybe become less readable but you've more control on the timings, moreover you've to understand what it's happening and that's not the feelings I've reading that code. I explain write a "*" and a "/" in VHDL mean inferr HARDWARE multiplicators and divisors that are a lot of logic cell (or hw dedicated cells) and their timings should be critical expecially if not in a synchronous process as this one.  Imo in writing VHDL, you must take in account all you're doing and what the compiler shall syntetize else when you'll download the code on an HW and it doesn't work you don't know what to look at.

[Altera_Forum]

Hello farrukh, 

few things for your attention: you are using a clock in your design. But instead of a clock why you are using DigitValid instead of a clock? please have a look at that. Does your digitvalid signal is a clock?   Second, when you use conversion functions such as conv_integer or conv_std_logic_vector please dont forget to include respective library. In your case, when you are converting integer, dont directly convert to std_logic_vector instead first convert either to signed or unsigned and then convert to std_logic_vector. please remember you are using std_logic_arith library. for better understanding please have a look at the following site for convertion functions:  http://dz.ee.ethz.ch/support/ic/vhdl/vhdlsources.en.html

[Altera_Forum]

Hello, 

  --- Quote Start ---  In your case, when you are converting integer, dont directly convert to std_logic_vector instead first convert either to signed or unsigned and then convert to std_logic_vector. please remember you are using std_logic_arith library.  --- Quote End ---    The suggestion is correct regarding std_logic_arith library, as the design also references std_logic_unsigned, all std_logic_vector is regarded as unsigned as well. Personally, I dislike std_logic_unsigned respecetively std_logic_signed cause you get difficulties when using signed and unsigned in combination and would do as you suggested. But the code creates well defined behaviour anyway.  Generally, with VHLD it's very unlikely that HDL compiler misunderstands your code and does something different to my opinion. With VHDL the compiler most likely complains about ambiguous types when you never would have thought of. So if the compiler accepts the code, you can be rather sure that no ambiguousities are left.  Regards, Frank

[Altera_Forum]

--- Quote Start ---  the / 300000000000 must be expected constant zero cause it overflows integer range.  --- Quote End ---    That worked! Thanks everyone for suggestions.