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Altera_Forum
Honored Contributor I
2,815 Views

No SDO file produced for Timing Simulation

I'm following the guide to get started with a MAX10 board: ftp://ftp.altera.com/up/pub/altera_material/16.1/tutorials/vhdl/quartus_ii_introduction.pdf

 

It's all very straightforward: I added some code, simulated using ModelSim-Altera, added a test vector and programmed the MAX10 development board which worked as expected. However, if I try and follow the 8.1.2 'Timing Simulation' section to verify the timing, I get the following error: 

 

Error (suppressible): (vsim-SDF-3196) Failed to find SDF file "test_max10_vhd.sdo".# vsim -novopt -c -t 1ps -sdfmax light_vhd_vec_tst/i1=test_max10_vhd.sdo -L fiftyfivenm -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.light_vhd_vec_tst# Error loading design Error loading design  

 

No *.sdo file containing timing information is produced in the build directories (I expected it to be in the \simulation\modelsim directory). 

 

In the section, the tutorial states:  

 

--- Quote Start ---  

Note: timing simulations are only supported by Cyclone IV and Stratix IV FPGAs. If your DE-series board does not have a Cyclone IV or Stratix IV FPGA, the result of a timing simulation will be identical to the functional simulation 

--- Quote End ---  

 

 

Are timing simulations not supported with MAX10? I thought a brief description of the design process is: write code, map pins to entities, test code with test bench (simulation), verify timing, program device, use signal tap...etc if required to debug target....etc 

 

If the above is true, how is the timing verified on MAX10?  

 

The other confusion is that in the tutorial it states to leave EDA tool settings to defaults, which is actually none. I set the Simulation tool ModelSim-Altera for the simulation to work, but left the Synthesis blank. When the Design Entry/Synthesis blank what's performing synthesis?
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3 Replies
Altera_Forum
Honored Contributor I
602 Views

EDA tools are meant to be 3rd-party-tools such as modelsim for simulation. 

As for synthesis quartus does that itself.  

quartus simulator if available is too basic compared to modelsim and Intel(Altera) is so embarrassed about it and stopped it. 

 

As to timing simulation I haven't done it all my life. I am happy with functional simulation + timing analysis using correct constraints. 

For some large projects timing simulation could take days to finish-just to give an idea.  

 

Timing simulation is favoured for very small safety critical projects.
Altera_Forum
Honored Contributor I
602 Views

https://www.altera.com/en_us/pdfs/literature/hb/qts/qts-qps-5v3.pdf 

 

Post-fit Standard Delay Output File (.sdo). Not supported for MAX 10 devices.
Altera_Forum
Honored Contributor I
602 Views

Hey, I'd just like to add some specifics to what skyjuice88 posted above. Max 10 does not support "Gate-level timing". This is stated on [pg 12 : table 1-2] in that pdf he linked to. This is from the official Altera guide quartus prime standard edition handbook volume 3: verification (https://www.altera.com/en_us/pdfs/literature/hb/qts/qts-qps-5v3.pdf). 

 

I thought I'd add this in case that link broke in the future.  

 

I was having trouble with this as well. We got these "DE-10 Lite" boards for a class at the University of Florida. We're supposed to use .sdo files in ModelSim, but our boards can't generate it according to the above. To solve this, I ended up running the compilation for a random Max V device to get the .sdo file.
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