No feasible entries for subprogram read

Altera_Forum · ‎09-11-2016

I don't understand: I have used this piece of code over and over again, it has always worked. Instead, now I can't get rid of the error No feasible entries for subprogram "read".

Any idea would be of great help! Thank you!

read_data: process(clk)
    file fp_in : text open READ_MODE is "./exps.txt";
    variable line_in : line;
    variable x, y : std_logic_vector(w-1 downto 0);
    begin
        if clk'event and clk='1' then
          if not endfile(fp_in) then
        readline(fp_in, line_in);
        read(line_in, x);
        exp_a <= x;
        read(line_in, y);
        exp_b <= y;
      end if; 
        end if;
    end process;

Altera_Forum · ‎09-12-2016

did you include the std_logic_textio library, or use VHDL 2008 compile options?

I assume this is simulation code, because this code cannot be synthesised.