Node: emi_addr[0] was determined to be a clock

[Altera_Forum]

hi,  

An interesting warning as fllows is beyond my understading.     --- Quote Start ---  Warning: Node: emi_addr[0] was determined to be a clock but was found without an associated clock assignment.  --- Quote End ---  The fllowing is part of my RTL codes ,related to this warning;    --- Quote Start ---   input clk_100,reset; input wire emi_cs,emi_we,emi_oe; input [9:0]emi_addr; input [15:0]emi_data;  wire [15:0]ssm_addr_eth; reg [5:0]emi_cnt_eth; always@(posedge clk_100 or negedge reset) begin  if(!reset)  emi_cnt_eth<=0;  else if(!emi_cs && !emi_we && emi_oe)  emi_cnt_eth<=emi_cnt_eth+6'h1;  else emi_cnt_eth<=0; end   assign ssm_addr_eth[15:0] = (!emi_cs && emi_oe && !emi_we && emi_cnt_eth==6'h4 && emi_addr==10'h060)?emi_data:ssm_addr_eth[15:0]; always@(posedge clk_100 or negedge reset) begin  if(!reset)   ssm_addr_ready_eth<=0;   else if(!emi_cs && emi_oe && !emi_we && emi_cnt_eth==6'h0f && emi_addr==10'h061)  ssm_addr_ready_eth<=1;   else ssm_addr_ready_eth<=0; end   --- Quote End ---  the emi's signals can be stable for 31 cycles of 100Mhz clock.   I can't imagine how can the compiler think the address signals as a clock?    By the way,these days I am confused by the timing analysis.The report say ,"Critical Warning: Timing requirements not met".However,sometims this warning may disappear.Perhaps my design is unstable.The slack is changeable with the same RTL code. In addition,the slack is negetive in the same clock domain.And sequential logics accounts for most of my HDL design.   best regards, yang

[Altera_Forum]

Weird. 

Fire up the RTL Netlist viewer and try to find any place where emi_addr[0] drives a flip-flop's clock pin or so.  Compilations are driven by a random seed, so you can expect small changes from one to the other. Is it negative setup or hold slack?

[Altera_Forum]

--- Quote Start ---  Weird. Fire up the RTL Netlist viewer and try to find any place where emi_addr[0] drives a flip-flop's clock pin or so.  Compilations are driven by a random seed, so you can expect small changes from one to the other. Is it negative setup or hold slack?  --- Quote End ---    dear,rbugalho   RTL view,see the attachment.the address signal is fed to the comparator at the first level logic.    it's holdup slack now,and sometimes a setup slack report errors. the error node(hold up ) :    --- Quote Start ---   network|IP|DATA_Control|Over_IP|OP_1|ONE|PTS|LAST_OUT|FIFO_TX|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_07i1:auto_generated|delayed_wrptr_g[7]   --- Quote End ---  

[Altera_Forum]

assign ssm_addr_eth = (!emi_cs && emi_oe && !emi_we && emi_cnt_eth==6'h4 && emi_addr==10'h060)?emi_data:ssm_addr_eth; 

 I'm not sure if it's what't causing you trouble, but this piece of code will infer latches.  That's a dual clock FIFO. Which are the clocks?

[Altera_Forum]

--- Quote Start ---  assign ssm_addr_eth = (!emi_cs && emi_oe && !emi_we && emi_cnt_eth==6'h4 && emi_addr==10'h060)?emi_data:ssm_addr_eth;I'm not sure if it's what't causing you trouble, but this piece of code will infer latches.  That's a dual clock FIFO. Which are the clocks?  --- Quote End ---    dear,rbugalho  I use wire instead of register to save logic resources.When I compared the report,it seems that this make no sense.I just replace flop-fiops by latches.    wrclk=27Mhz ,rdclk=100Mhz,and the wrong launch and latch clock is 27Mhz.the input data width is 8bit,and output one is 32bit,depth=2048*8 byte   thanks, yang