Node finder not finding Nodes(Quartus II)

[Altera_Forum]

So, heres my question. I've just started working with QII for an introductory college course I'm currently takeing and I'm running into an problem when trying to simulate one of my designs using a vector waveform file. This particular assignment requires the student to create a ripple carry adder (that adds a single 4 bit number) from half adders, Here is my error:  

 I've created a design for a half adder that I'll be using in an assignment. I made this design using a block diagram schematic file and simple logic gates. I compiled the design and it ran through with no errors. I saved the file under the name half_adder. After designing the adder I created a symbol file from it using File>Create/Update>Create Symbol Files for Current File. I open a new block diagram schematic file and input several instances of the adder and wire them together and give them input pins, i save and compile the file and it runs through. I name this file full_adder. Now i would like to simulate my design using a vector waveform file. So i create a new file and try to use the node finder to find the input and output nodes for the ripple carry adder file I created. When i use the node finder, even when i set the pin selection box to all, only the pins from my original half adder file come up. No pins from the other file composed of symbols are there. Also, it may be of note that the box labeled look in (in the node finder) only has one file name, half_adder. I'm not sure what I'm doing wrong but there is obviously something going on.   Sorry if this is something really simple, our teacher for this class doesn't really do a whole lot of teaching (most of his time is spent on his research, teaching is just a requirement for him). I also looked over the forums and could not find anything related to it.

[Altera_Forum]

Looks like, full_adder hasn't been set as the project's design top and was actually not compiled. You can check the actual project structure in the hierarchy view.

[Altera_Forum]

--- Quote Start ---  So, heres my question. I've just started working with QII for an introductory college course I'm currently takeing and I'm running into an problem when trying to simulate one of my designs using a vector waveform file. This particular assignment requires the student to create a ripple carry adder (that adds a single 4 bit number) from half adders, Here is my error:   I've created a design for a half adder that I'll be using in an assignment. I made this design using a block diagram schematic file and simple logic gates. I compiled the design and it ran through with no errors. I saved the file under the name half_adder. After designing the adder I created a symbol file from it using File>Create/Update>Create Symbol Files for Current File. I open a new block diagram schematic file and input several instances of the adder and wire them together and give them input pins, i save and compile the file and it runs through. I name this file full_adder. Now i would like to simulate my design using a vector waveform file. So i create a new file and try to use the node finder to find the input and output nodes for the ripple carry adder file I created. When i use the node finder, even when i set the pin selection box to all, only the pins from my original half adder file come up. No pins from the other file composed of symbols are there. Also, it may be of note that the box labeled look in (in the node finder) only has one file name, half_adder. I'm not sure what I'm doing wrong but there is obviously something going on.   Sorry if this is something really simple, our teacher for this class doesn't really do a whole lot of teaching (most of his time is spent on his research, teaching is just a requirement for him). I also looked over the forums and could not find anything related to it.  --- Quote End ---    Hi,  it lookslike that your project is a small one. Can you post it in the forum. I will have a brief look to it.  Kind regards  GPK

[Altera_Forum]

--- Quote Start ---  Looks like, full_adder hasn't been set as the project's design top and was actually not compiled. You can check the actual project structure in the hierarchy view.  --- Quote End ---    Thanks, that turned out to be my problem in the end. I was unaware that you needed to set it as the top level entity. As in regards to the earlier post, what do you mean by post my project. Is there a way to post files in these forums? The actual project is to design a stopwatch that outputs to a seven segment display that will output to an fpga board, using dff's to form a register, the adder circuit, a frequency divider, and several other parts. I dont know if that would be too large.   As of now i'm almost done however when i compile i keep getting two warnings, Firstly that "Warning: Output pins are stuck at VCC or GND", and also that "Warning: Design contains 3 input pin(s) that do not drive logic". Then when i try to simulate my design those outputs are non responsive. Are there any general causes for these warnings i could look at or are they fairly specific.

[Altera_Forum]

--- Quote Start ---  Thanks, that turned out to be my problem in the end. I was unaware that you needed to set it as the top level entity. As in regards to the earlier post, what do you mean by post my project. Is there a way to post files in these forums? The actual project is to design a stopwatch that outputs to a seven segment display that will output to an fpga board, using dff's to form a register, the adder circuit, a frequency divider, and several other parts. I dont know if that would be too large.   As of now i'm almost done however when i compile i keep getting two warnings, Firstly that "Warning: Output pins are stuck at VCC or GND", and also that "Warning: Design contains 3 input pin(s) that do not drive logic". Then when i try to simulate my design those outputs are non responsive. Are there any general causes for these warnings i could look at or are they fairly specific.  --- Quote End ---     Hi,  there are two ways to post your project. You can generate an project archive with quartus or you can put all your stuff in a zip-file.   Under the window for your post you find Additional Options. Press "Manage Attachments" and upload your archive or zip-file.  Kinf regards  GPK