Not able to get the 3.3V peak to peak from PLL generated output signal

[Pooja_03]

Hi,

I have generated a PLL (ALTPLL) IP in Quartus Lite software for the MAX10 FPGA (10M50DAF484C6GES). In the IP configuration, I set the input frequency to 50 MHz and generated an output frequency of 100 MHz. In my RTL top file, I mapped the PLL's generated output signal to a GPIO pin on the DECA board. I specified both the input clock and GPIO pin's I/O standard as 3.3V LVCMOS, so I expected to see a 3.3V peak-to-peak voltage on the oscilloscope.

However, when I measured the output, I observed that the peak-to-peak voltage was lower than 3.3V (approximately 3V). Additionally, as I increased the output frequency, the peak-to-peak voltage further decreased. For instance, at 250 MHz, the voltage unexpectedly decreased to around 1V, which is lower than the expected 3.3V limit. Ideally, the peak-to-peak voltage should remain consistent for every output frequency.

Could you please help me understand why the peak-to-peak voltage is behaving this way, and suggest a solution to ensure a stable 3.3V peak-to-peak output?

Thank you 

Pooja 

[FvM]

Hi,

most likely an oscilloscope and probing problem. Depending on oscilloscope and probe parameters, you won't necessarily reproduce 3.3V square wave exactly.
Please give details about used oscilloscope and probe, also possible bandwidth reduction in oscilloscope channel setup. 
Which GPIO pin are you using, is there anything else connected to it except for the oscilloscope input?

[Pooja_03]

Hi,

We are using MAX10 (10M50DAF484C6GES) Deca Board for testing the output frequency from GPIO (pin V17, W18, Y6, W6). 

Scope details : - Tektronix MDO3024 Mixed domain oscilloscope (scope is fine because we have tested other designs as well).

we tried with different probe as well issue remains the same.

Please help us to understand where is the issue. 

PFA image for your reference.

Thank you 

[FvM]

Hi,
the waveform looks as expected, due to bandwidth limiting, the square wave is displayed as sine with reduced magnitude.
As far as I know, MDO3024 has 200 MHz channel bandwidth, correct me if I'm wrong. To reproduce a 100 MHz square wave, you need 500 MHz - 1 GHz bandwidth. Another possible issue can be capacitive pin loading by oscilloscope probe and low IO drive strength.
Realistically, you most likely don't have the measurement tools to visualize 100 or even 250 MHz FPGA output signal.

[AqidAyman_Intel]

Hello,

I wish to follow up, with the answer provided, do you have any more questions on this?

Regards,

Aqid

[AqidAyman_Intel]

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