On-chip memory clear questions

[MinzhiWang]

Hi,

We used many kinds of memories in FPGA logic design. RAM, ROM and FIFO. We can use MIF or HEX files to inialize on-chip RAM or ROM.

Now we encounter situation: we want to clear on-chip RAM in real time. We thought to use system reset signal to clean entire RAM field. However, we read RAM UG and got that the Syn or Asny clear port only clean the RAM's Q port. The clear port seems can't clean RAM's inside internal space.

I just want to confirm if the RAM can have the same clear function as the  FIFO? We can clean full FIFO space by using the clear port.

Thanks

[FvM]

Hi,
IMHO there's no other way to clear RAM content than writing zero sequentially to all locations. FIFO clear works differently, it resets read and write pointers, present FIFO RAM content is maintained but not visible externally.

[MinzhiWang]

Hi FvM,

I appreciate that you reply this post so quickly. Now I'm sure that I understand the UG and your comments.

For the on-chip RAM usage, i also have other questions to dicuss here. Our device is of Cyclone 10 GX. We met on chip memory exhausted issue. Compilation report give us not only error info, also several other infos as following:

Info(170034): Selected device has 587 memory locations of type M20K block. The current design requires 626 memory locations of type M20K block to successfully fit.
Info(170033): Memory usage required for the design in the current device: 107% M20K block memory block locations required
Info(170043): The Fitter setting for Equivalent RAM and MLAB Paused Read Capabilities is currently set to Care. More RAMs may be placed in MLAB locations if a different paused read behavior is allowed.

We went to advance Fitter Settings page to change the setting of "Equivalent RAM and MLAB Paused Read Capabilities" from Care to don't care. Then the compilation was passed.

My question is what's the main effection of this setting?

You know, we implement many small size FIFO and RAM in our application. So we went to FIT report to check the place report and found one item as "Fits in MLABs".  Do the "Yes" indicators mean those blocks can be force to implemented thru MLABs? And you can't for the "No" corresponding blocks to realized by MLABs?

Thanks

[TingJiangT_Intel]

During synthesis analysis in Quartus, RAM can be implemented using either M20K or MLAB resources. However, because the structure and interface resources of M20K and MLAB are fixed, there is a limit to how many RAM blocks can be realized with a single M20K or MLAB. This limitation becomes more pronounced when implementing multiple small RAMs, as the available interface resources can be a significant constraint. Additionally, RAM settings—such as the number of read/write ports and enable ports—affect the required number of interfaces. As a result, the number of RAM blocks that can fit into one M20K or MLAB depends on the specific parameter settings of the RAM.

[MinzhiWang]

Hello TingJiang，

So for small size FIFO/RAM or ROM, we'd better force them to be realized by MLAB, if there are enough MLAB resource. Otherwise, these small size memory implementation may possible waste huge ratio RAM resource. Am I right?

Thanks

Best Regard

[TingJiangT_Intel · Accepted solution]

We'd recommend using M20K which is dedicated memory resource to realize RAM instead of MLAB. MLAB is mainly using for logic. It will consume more resource when using MLAB to implement RAM.