Hello,
I'm using LVDS receiver (LVDS_RX) to process ADC serial output data stream. LVDS_RX provides one output parallel clock, rx_coreclock, which is used for asyncronous FIFO's write clock. The FIFO's read side uses system clock.
When above logic is implemented, the system clock domain's reset signal is used on rx_coreclock domain. After full compilation, I get Setup and Recovery timing violation report.
Setup Timing Violation Report:
Recovery Timing Violation Report:
After I found that the reset was used in two different clock domain, I synchronized this reset signal from system clock domain to rx_coreclock domain. I thought this should resolve above two violations. However, only Setup timing violation was resolved.
Resolved Setup Timing：
The Recovery Timing violation still there.
Report Timing from TimeQuest for the Recovery:
As above image, the Recovery timing violation's From Node coming from system clock domain's reset signal. And "To Node" comes from re_coreclock domain's reset re-synchronized module's two inner nodes. Below is the re-synchronized module codes:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity reset_async_2_sync is
port (
clkin : in std_logic;
async_rst : in std_logic;
sync_rst : out std_logic
);
end reset_async_2_sync;
architecture rtl of reset_async_2_sync is
signal Sync_rst1,Sync_rst2: std_logic;
begin
process(clkin,async_rst)
begin
if async_rst='0' then--Async reset is ��0�� assert
Sync_rst1 <= '0';
Sync_rst2 <= '0';
elsif clkin'event and clkin='1' then
Sync_rst1 <= '1';
Sync_rst2 <= Sync_rst1;
end if;
end process;
sync_rst <= Sync_rst2;
end ;
So my question is how to resolve this recovery timing violation. Can i use set_false_path command to deal with it?
Thanks
Best Regard
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