Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Altera_Forum
Honored Contributor I
775 Views

OpenCL 15.1 vs 17.1 with DE1-SoC (Cyclone V SoC)

Hi, 

 

I have designed a circuit with OpenCL using Quartus 15.1 in DE1-SoC board, the resources utilisation was fine (about 53%), I take the same cl file and compile it with OpenCL using Quartus 17.1, it cannot fit on the device and it takes more than the existing resources on the FPGA (about 130%). 

 

Is there any explications? 

How can I resolve this problem? 

 

Thanks
0 Kudos
2 Replies
Altera_Forum
Honored Contributor I
17 Views

Did you place and route the design using Quartus v17.1, or are you judging that it is not going to fit based on the area estimation report? The area estimation in v17.0 and v17.1 seems to have gotten more inaccurate compared to the previous versions, and designs that are predicted to overutilize FPGA resources might actually fit. 

 

If, however, you are place and routing the design and it doesn't fit, then this could be part of the regressions introduced in v17.0; Altera made significant changes in the OpenCL compiler in v17.0, which seem to decrease performance and increase area usage in some cases. If this is indeed what is happening in your case, I recommend trying v16.1.2. In my experience, that is the most efficient version of the compiler in terms of performance and area usage. Furthermore, I recommend you report your issue to Altera so that they know the new versions of the compiler are performing worse than the older ones.
Altera_Forum
Honored Contributor I
17 Views

 

--- Quote Start ---  

Did you place and route the design using Quartus v17.1, or are you judging that it is not going to fit based on the area estimation report? The area estimation in v17.0 and v17.1 seems to have gotten more inaccurate compared to the previous versions, and designs that are predicted to overutilize FPGA resources might actually fit. 

 

If, however, you are place and routing the design and it doesn't fit, then this could be part of the regressions introduced in v17.0; Altera made significant changes in the OpenCL compiler in v17.0, which seem to decrease performance and increase area usage in some cases. If this is indeed what is happening in your case, I recommend trying v16.1.2. In my experience, that is the most efficient version of the compiler in terms of performance and area usage. Furthermore, I recommend you report your issue to Altera so that they know the new versions of the compiler are performing worse than the older ones. 

--- Quote End ---  

 

 

Thanks for reply, 

 

In fact in the 15.1 the circuit is compiled and tested on the board, but in the 17.1 an error message says that the circuit doesn't fit in the device. 

Surprisingly for another circuit has the opposite situation I have small area in the 17.1 against 15.1 

I'll try to rewrite and optimise it and see if this resolve the problem. 

 

Thank you