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OpenCL project compilation is taking forever to finish

Honored Contributor I

Currently I am working on an openCL project. It works in simulation, but when I compiled for hardware using Quartus II on Arria 10 soc, it could not finish even with a whole weekend! (it's estimated to consume 76% DSP and 78% BRAM) Could the reason be that the generated verilog file is not synthesizable?

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