Optimisation issues

[Altera_Forum]

Hi, is there any way to find out WHY Quartus is optimising away stuff? I know I've almost certainly got something wrong in my VHDL, but I've found that several of my signals/registers are 'missing' on the final output. If I look at the RTL netlist, they're there, but in the finished output, they've gone (they don't work in the programmed FPGA, and SignalTap doesn't know about them), so obviously the optimiser has decided they're not used. 

 So, is there anywhere I can look to see why? Eg, outputs not used, inputs not connected, state not possible or something like that? What I'm doing at the moment is just changing, adding & removing bits in the hope that I can get some clues, but it seems like there must be a better way :-)  (I can't really post the source here because it's a little part of a complex project, so will be complex to extract in a way that doesn't possibly "fix" the problem in that sample).

[Altera_Forum]

Go through the warnings generated by the synthesizer. If you have lots of them, you can do a search with your signal name.

[Altera_Forum]

That's the first thing I did - there's nothing at all with the signal name in the synthesizer output :-( 

 Now, it might be that it's not optimising the registers/signals away, but there's some other reason SignalTap can't find them. If I search for 'all signals' then they're there, but not if I search in post-fitting. If I select one in 'all signals', then it appears in red, which I guess means that it can't display its contents.  (It's not working in the programmed FPGA either, where other, similar constructs are, which, along with not appearing in SignalTap may have made me come to the wrong conclusion)

[Altera_Forum]

--- Quote Start ---  That's the first thing I did - there's nothing at all with the signal name in the synthesizer output :-(  Now, it might be that it's not optimising the registers/signals away, but there's some other reason SignalTap can't find them. If I search for 'all signals' then they're there, but not if I search in post-fitting. If I select one in 'all signals', then it appears in red, which I guess means that it can't display its contents.  (It's not working in the programmed FPGA either, where other, similar constructs are, which, along with not appearing in SignalTap may have made me come to the wrong conclusion)  --- Quote End ---     when adding nodes to signaltap it asks if you want them before compilation(design entry) or later. Have you tried that.  Due to optimisation, register retiming, duplication etc some nodes cease to exist unless you want them stay.

[Altera_Forum]

Yes, if I choose Design Entry (all signals) then they're there, but appear in red. 

 I'm wondering if (the name of) a signal which is just there to pass a data from one component to another will just be deleted because it's the same as the source component's output signal.

[Altera_Forum]

you then need to recompile it. It cpould be the "signaltap-presynthesis" option

[Altera_Forum]

It's not there either - the only place I can find it is in the 'Design Entry (all signals)' list. If I select any of the others (including signaltap-presynthesis) the signal is not found. 

 (I'm recompiling it after every thing I try, so it's not a quick job :-) )

[Altera_Forum]

BTW - I think I've found why the FPGA isn't working, and it wasn't an optimisation issue, it was a timing one. It'll have to wait until I get home tonight before I can test it out, but the mistake I've found makes sense. 

 But I'm still not sure if I should have been able to do what I wanted in SignalTap - if I had been, I think I'd have found the problem sooner. I think my confusion with that lead me to wasting time investigating in the wrong places. I think I may need to experiment a bit more to see if I can work out how SignalTap is handling the signal naming.

[Altera_Forum]

--- Quote Start ---  BTW - I think I've found why the FPGA isn't working, and it wasn't an optimisation issue, it was a timing one. It'll have to wait until I get home tonight before I can test it out, but the mistake I've found makes sense.  But I'm still not sure if I should have been able to do what I wanted in SignalTap - if I had been, I think I'd have found the problem sooner. I think my confusion with that lead me to wasting time investigating in the wrong places. I think I may need to experiment a bit more to see if I can work out how SignalTap is handling the signal naming.  --- Quote End ---    timing problems + signaltap is a very bad mixture since signaltap logic adds more logic and may mislead you if timing is not right.  Modelsim testbench is best to check functionality and add to it a successul STA closure and it should work first time in the chip...with a bit of prayer!  If you have to use signaltap make sure design passes timing. Use minimum space for testing and you can force nodes to stay using keep attribute or connect to unused pins or other measures specific to signaltap tool itself (which I am no expert).

[Altera_Forum]

No, SignalTap would have been fine. It wasn't a 'metastable' type timing problem, it was a me-doing-things-in-the-wrong-order type timing problem :-) So, it would have shown that. I was sending data onto an external CPU's data-bus at totally the wrong time in its clock cycle (200ns too early) so it wasn't seeing it.  

 (Modelsim is a different issue - I'm struggling with that because I'm using a NIOS II, SDRAM, etc and really don't know what if/how I can simulate that ;-) For simpler components I've managed and it's fine, but in this case it was an interface between the NIOS II and an external CPU which was the problem, so simulating that accurately wasn't going to be trivial for a noob like me... )

[Altera_Forum]

I forgot that you only get a warning when the synthesizer optimizes a signal away because it doesn't drive any signal. In the other cases, signals can be optimized away without warning. For example: 

a<= b and c; b <= d and e;In this case (provided b isn't used somewhere else) the simulator will generate the a signal using a single LUT and the c,d and e signals. b will be optimized away. If you want to read it from Signaltap you will need to put a "preserve" attribute on the signal to prevent if from going away (IIRC connecting it to Signaltap in pre-synthesis isn't enough).

[Altera_Forum]

Thanks - I thought that might be what's happening.