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Valued Contributor III
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Optimum compressor (carry-save adder) for Arria V architecture?

Can anybody point me to a reference like the Advanced Synthesis Cookbook for the Arria V? 

 

Specifically, I'm looking for what the optimum compressor implementation is. The Advanced Synthesis Cookbook likes 6-to-3 compressors very much for the Stratix series. 

 

However, does this also hold for the Arria V and should they be implemented the same way? 

 

Thanks.
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Valued Contributor III
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Well, after doing a documentation dive on the Stratix series and the Arria V, it seems like the Arria V has similar arithmetic blocks. So, I assumed that the same compressor system holds. 

 

This *seems* to be okay. I haven't gotten horrible timing results, but I'm certainly far from knowing whether this is optimal or not. Just thought I would update for some future person.
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Valued Contributor III
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The logic blocks are now fairly consistent across the whole family Cyclone-arria-stratix, so whats good for one is usually good for the others.

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