Output signal only occurs when a rising edge is triggered, but need constant output.

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Output signal only occurs when a rising edge is triggered, but need constant output.

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Hi,

So I have developed a code, based on a reference design provided by caen, for a v1495 vme board. I need to pass through some signals from port A to port G, however there is only a short pulse ~20 ns created in port G only when there is a rising edge on the port A input. I have checked other possible reasons why this would be occurring, but I have narrowed it down to be a problem with my vhdl design. I like to think that the issue lies in the way my architecture is structured. I have attached the main part of the design file if you prefer to look at it. If you require more clarification on this issue, please let me know, however bear in mind that I am an absolute beginner at this.

Kind regards.

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