PCIE example designs with external PHY without source synchronous transmit clock

Intel® Quartus® Prime Software

Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)

PCIE example designs with external PHY without source synchronous transmit clock

965 Views

I went through the MegaWizard for PCIE targeting the external PHYs, TI XIO1100 and NXP PX1011A. However, each of these have source synchronous transmit clock. I'm trying to find a sample external PHY design which doesn't have the transmit clock so that I can review the timing constraints. I'd like to see how the Gen2 250 MHz pipe clock and TX data is handled by the design (probably a PLL with phase shift) and specifically what the timing constraints look like for the TX signals. Are there such designs within the MegaWizard or elsewhere in Altera?

Link Copied

0 Replies

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.