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Trying to generate a PCIe endpoint example design (QPP 18.1.0, Stratix 10 1SX085HN2F43I2VG), getting an error:
Error: add_fileset_file: No such file C:/Users/My.Name.Here/AppData/Local/Temp/alt9571_2686104493968254145.dir/0002_pcie_s10_hip_avmm_bridge_0_gen/ip/pcie_example_design/pcie_example_design_DUT/altera_pcie_s10_hip_avmm_bridge_181/sim/aldec/altera_pcie_s10_64avmm_adapter/altera_pcie_s10_adapter_rx.v/altera_pcie_s10_adapter.v
I am aware of the issue regarding path length:
(https://www.intel.com/content/www/us/en/support/programmable/articles/000087662.html),
and I had that problem addressed by the local IT folks. But I am still getting the same error.
Is there another workaround for this?
Thanks.
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Hi,
This issue is caused by filename length limitation of Windows OS. You can generate the example design with Linux OS, which can be used on Windows OS as well. Or you can try with the following workaround on Windows OS. Thanks.
https://docs.microsoft.com/zh-cn/windows/win32/fileio/maximum-file-path-limitation?tabs=cmd
Regards,
Wincent_Intel
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Hi,
I wish to follow up with you about this case.
Do you have any further questions on this matter ?
Else I would like to have your permission to close this forum ticket
Regards,
Wincent_Intel
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Hi
We have not hear from you and this Case is idling. It is not recommended to idle for too long.
Therefore following our support policy, I have to put this case in close status. My apologies if any inconvenience cause
Hence, This thread will be transitioned to community support.
If you have a new question, feel free to open a new thread to get support from Intel experts.
Otherwise, the community users will continue to help you on this thread. Thank you
If your support experience falls below a 9 out of 10, I kindly request the opportunity to rectify it before concluding our interaction. If the issue cannot be resolved, please inform me of the cause so that I can learn from it and strive to enhance the quality of future service experiences.
Regards,
Wincent_Intel
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