PISO (4 bit parallel in serial out shift reigster)

[Altera_Forum]

Hello, I'm trying to create a simple 4-bit parallel in and serial out shift register.  

 So far, here is what I have:    --- Quote Start ---  LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_unsigned.all;   ENTITY shift IS PORT ( sout : out std_logic; p : IN std_logic_vector (3 DOWNTO 0); clr, sin, load : IN std_logic; clk : IN std_logic ); END shift;  ARCHITECTURE bhv OF shift IS signal qlatch: std_logic_vector(3 downto 0); begin  process (CLR, CLK) begin   if (clr = '1') then qlatch <= "0000";  elsif (CLK'event and CLK='1') then  if (LOAD='0') then  qlatch <= '0' & p(3 downto 1); end if; end if;  end process; sout <= qlatch(3); end bhv;   --- Quote End ---    Now, the code itself compiles; however, when I try to test its functionality on my board (EPM7128SLC84-15), nothing happens.  If anyone has any suggestion or point out any errors, it would be greatly appreciated. Thank you.

[Altera_Forum]

--- Quote Start ---  Hello, I'm trying to create a simple 4-bit parallel in and serial out shift register.   So far, here is what I have:    Now, the code itself compiles; however, when I try to test its functionality on my board (EPM7128SLC84-15), nothing happens.  If anyone has any suggestion or point out any errors, it would be greatly appreciated. Thank you.  --- Quote End ---    My guess, I believe it should be: sout <= qlatch(0);

[Altera_Forum]

--- Quote Start ---  My guess, I believe it should be: sout <= qlatch(0);  --- Quote End ---    Didn't work.  I believe that line just takes that specific bit in the 4 bits, but doesn't actually shift.

[Altera_Forum]

--- Quote Start ---  Didn't work.  I believe that line just takes that specific bit in the 4 bits, but doesn't actually shift.  --- Quote End ---    but you shift statement is from msb to lsb i.e. bit3 starts as zero then bit2 then bit1 then bit0. So bit 3 will always be zero

[Altera_Forum]

--- Quote Start ---  but you shift statement is from msb to lsb i.e. bit3 starts as zero then bit2 then bit1 then bit0. So bit 3 will always be zero  --- Quote End ---    you also need to load qlatch with input first at load then start the shift. You are just assigning input 3 bits to qlatch