PLL Dynamic Reconfiguration in Altera Stratix V (Warning (15104): bonding design?)

[Altera_Forum]

Hi, 

  In our project using a Stratix V board, we need to be able to modify the clock frequency during run time with as much precision as possible. Our solution is to provide the parameters used to reconfigure the PLL by providing the appropriate N, M and C value from software. The valid settings are obtained by performing an exhaustive search on the possible values of N, M and C and finding the closest based on the following equations:  C = Fin*M/(Fout*N) ==> Fout = Fin*M/(N*C)   The programming of a PLL is done via FSM by writing appropriate values to PLL reconfiguration controller based on the information provided in http://www.altera.com/literature/an/an661.pdf. The PLL controller unit, in turn, programs the PLL unit which intends to produce an expected output.  The FSM used to program the PLL controller behave as followed:  STATE(rst) -> go to STATE(wait_req) when <locked> signal is high from PLL.  STATE(wait_req) -> go to STATE(wait_rdy) when <prog_request> signal is high.  STATE(wait_rdy) -> go to STATE(cfg_mode) when <waitrequest> is low and <locked> is high.  STATE(cfg_mode) -> Programs the mode to *waitrequest* and go to STATE(cfg_n).  STATE(cfg_n) -> Programs n and go to STATE(cfg_m).  STATE(cfg_m) -> Programs m and go to STATE(cfg_c).  STATE(cfg_c) -> Programs c and go to STATE(cfg_start).  STATE(cfg_start) -> Programs starts and go to STATE(wait_unlocked).  STATE(wait_unlocked) -> waits until the <locked> signal is low and go to STATE(wait_locked)  STATE(wait_locked) -> waits until the <locked> signal is high and go to STATE(cpl)  STATE(cpl) -> sends a completion signal and go to STATE(wait_req)   Note: Other parameters are not touched. Assume that the PLL is operating in the INTEGER mode and waitrequest mode is active by default.   The above process seems to work fine in simulation but only to certain settings in hardware. The completion flag can only become active to only small values of N, M and C.  Higher values seem to get ignored by the module (the FSM gets stuck somewhere).     Furthermore, I also noticed that the following warnings are shown:   ==== Quartus 13.0sp1 ==== Info (125069): Default assignment values were changed in the current version of the Quartus II software -- changes to default assignments values are contained in file e:/altera/13.0sp1/quartus/bin64/assignment_defaults.qdf Warning (15104): Quartus II software detected a bonding design. Reconfiguration is not supported for Bonded designs and MIF is not created for this design. =====================     1. Is it possible to perform the PLL reconfiguration process as stated above?   If yes, am I required to program other parameters (Franctional value, Bandwidth, Charge pump) as well? 2. Is the warning normal? If not, how do I resolve the issue?   Thanks in advance Regards, Ekawat   EDIT: rewrote the post to make it clearer.