PLL Issue

[Altera_Forum]

I have a simple design in a StratixIII that has a pll. The pll is set to run with an input clock of 125MHz and an output clock of 125MHz.  

 TimeQuest says the device timing is OK with no errors. The design runs on a board at 100MHz but not at 125MHz.   When I try a post synthesis gate simulation, and drive a 125MHz clock input to the PLL, I get the following message from Modelsim  Input clock freq. is under VCO range. StratixIII PLL may lose lock.  This message is not there when I change the input clock to 100MHz, the PLL is in LOCK.   Below is the PLL report from the fit report.  Why does the design fail at 125MHz when the timing says it should be OK, and why the message in simulation?   SDC pin name ; sys_pll|altpll_component|auto_generated|pll1 ; ; PLL type ; Top/Bottom ; ; PLL mode ; Normal ; ; Compensate clock ; clock0 ; ; Compensated input/output pins ; -- ; ; Switchover type ; -- ; ; Input frequency 0 ; 125.0 MHz ; ; Input frequency 1 ; -- ; ; Nominal PFD frequency ; 125.0 MHz ; ; Nominal VCO frequency ; 625.0 MHz ; ; VCO post scale ; 2 ; ; VCO frequency control ; Auto ; ; VCO phase shift step ; 200 ps ; ; VCO multiply ; -- ; ; VCO divide ; -- ; ; DPA multiply ; -- ; ; DPA divide ; -- ; ; DPA divider counter value ; -- ; ; Freq min lock ; 60.02 MHz ; ; Freq max lock ; 130.04 MHz ; ; M VCO Tap ; 0 ; ; M Initial ; 1 ; ; M value ; 5 ; ; N value ; 1 ; ; Charge pump current ; setting 1 ; ; Loop filter resistance ; setting 28 ; ; Loop filter capacitance ; setting 0 ; ; Bandwidth ; 1.19 MHz to 1.7 MHz ; ; Bandwidth type ; Medium ; ; Real time reconfigurable ; Off ; ; Scan chain MIF file ; -- ; ; Preserve PLL counter order ; Off ; ; PLL location ; PLL_B1 ; ; Inclk0 signal ; CLK_G0P ; ; Inclk1 signal ; -- ; ; Inclk0 signal type ; Dedicated Pin ; ; Inclk1 signal type ; -- ; +-----------------------------