PLL dedicated output pin in LVDS mode

[Altera_Forum]

Quartus v9.1 sp2 

EP3C16F484C8 and EP3C40F780C8  Hi - I'm unable to assign an LVDS pin pair to a PLL dedicated output, however a single-ended pin can be assigned. The test project contains only a single PLL, input & output pins, and an altclkctrl_external.   Also note, the MegaWizard for a c3 PLL doesn't show the e[3..0] clock outputs, only c[4..0], and the wizard has no specific option for accessing the extclk outputs. I'm presuming Quartus uses c0 or e0 depending on how the pin assignment is made, or on whether the routing is explicitly made using altclkctrl (global or external).  Here's what I've tried:  1) When an LVDS pin is connected directly to c0 the PinPlanner won't let me make a pin number assignment to any of the PLLx_CLKOUT pins, warning about an incompatible I/O standard. And if no pin number assignment is made, the fitter doesn't use the dedicated PLLx_CLKOUT pins and I get this warning: **************** Warning: PLL "PLL:inst|altpll:altpll_component|PLL_altpll:auto_generated|pll1" output port clk[0] feeds output pin "clk_out_lvds~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance ****************   2) Connecting c0 through altclkctrl_external to an LVDS pair gives an error: **************** Error: Can't assign node "PLL:inst|altpll:altpll_component|PLL_altpll:auto_generated|wire_pll1_clk[0] (driving Clock control block altclkctrl_external:inst1|altclkctrl_external_altclkctrl_voi:altclkctrl_external_altclkctrl_voi_component|clkctrl1)" to any location Error: Can't assign node "PLL:inst|altpll:altpll_component|PLL_altpll:auto_generated|wire_pll1_clk[0] (driving Clock control block altclkctrl_external:inst1|altclkctrl_external_altclkctrl_voi:altclkctrl_external_altclkctrl_voi_component|clkctrl1)" to location PLL_1 Error: Can't assign node "PLL:inst|altpll:altpll_component|PLL_altpll:auto_generated|wire_pll1_clk[0] (driving Clock control block altclkctrl_external:inst1|altclkctrl_external_altclkctrl_voi:altclkctrl_external_altclkctrl_voi_component|clkctrl1)" to location counter C0 of PLL_1 Error: Can't use clock type Global Clock at location CLKCTRL_G3 for clock control block or source node altclkctrl_external:inst1|altclkctrl_external_altclkctrl_voi:altclkctrl_external_altclkctrl_voi_component|clkctrl1 with clock type External Clock Output -- clock types do not match Error: Can't use clock type Global Clock at location CLKCTRL_G0 for clock control block or source node altclkctrl_external:inst1|altclkctrl_external_altclkctrl_voi:altclkctrl_external_altclkctrl_voi_component|clkctrl1 with clock type External Clock Output -- clock types do not match Error: Can't assign node "PLL:inst|altpll:altpll_component|PLL_altpll:auto_generated|wire_pll1_clk[0] (driving Clock control block altclkctrl_external:inst1|altclkctrl_external_altclkctrl_voi:altclkctrl_external_altclkctrl_voi_component|clkctrl1)" to location CLKCTRL_PLL1E0 Error: Pin AA3 does not support I/O standard LVDS for clk_out_lvds ****************   What am I doing wrong? I can make the dedicated assignment either way without warnings if the pin is single-ended, but not if it's LVDS.  A simple test project is attached.