Parallel Flash Loader VS JTAG Stratix IV

[Altera_Forum]

Is there a way to get the Fast Passive Parallel flash loader to cooperate with JTAG programming? 

 I have:  - a CPLD with the PFL installed, it works, and loads the FPGA - JTAG to the FPGA..  When I try to load an image into the FPGA via JTAG, it finishes loading, then the CPLD wakes up and reloads the FPGA from the flash image, wiping out my debug image.. Any thoughts as to how to make these two play nice?  Currently I replace the CPLD image with a dummy one that doesn't contain the PFL module in it, but this is not a workable method..

[Altera_Forum]

You can add en pin to CPLD or erase CPLD at all. But I think is something wrong with you design.

[Altera_Forum]

Solved - yes it was a bug in my design.  

 I had a signal contention issue in the FPGA design, and my on board power monitor circuit was resetting the board when the FPGA finished loading, causing it to reboot and reload from NOR flash.   Fixed that, and now both JTAG and the PFL work together nicely.