Parameter mapping in QSYS

Intel® Quartus® Prime Software

Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)

Parameter mapping in QSYS

1,013 檢視

Hi,

does anybody know how is the mapping from HDL Parameters to a signal width in QSYS component editor is done?

I try to implement a component with generic port widths. I have defined the parameter WIDTH in the HDL Parameters Tab (parameters.jpg). I will use it in to specify the signal width in signals tab but QSYS generates an error if I put the string "WIDTH" in the Width column (signals.jpg).

According Quartus II Handbook Version 11.0 Volume 1: Design and Synthesis, page 6-13 it should be possible but how?

Jens

連結已複製

0 回應

週一至週五提供社區支援。請點選這裡查看其他聯絡方式。

Intel 不會確認所有解決方案，包括但不限於可能出現在這個社群的任何檔案傳輸。因此，Intel 不承諾任何明示與暗示保證，包括但不限於適售性的暗示保證、適用於特定用途和無侵權，以及肇因於履行過程、交易過程或商業慣例的任何保證。

如需有關編譯器最佳化更完整的資訊，請參閱最佳化公告.