Parameter mapping in QSYS

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Parameter mapping in QSYS

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Hi,

does anybody know how is the mapping from HDL Parameters to a signal width in QSYS component editor is done?

I try to implement a component with generic port widths. I have defined the parameter WIDTH in the HDL Parameters Tab (parameters.jpg). I will use it in to specify the signal width in signals tab but QSYS generates an error if I put the string "WIDTH" in the Width column (signals.jpg).

According Quartus II Handbook Version 11.0 Volume 1: Design and Synthesis, page 6-13 it should be possible but how?

Jens

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