Parametrized altsyncram using design compiler and quartus

[Altera_Forum]

Hi! 

 Is there a way to synthesize an vhdl design that instantiates parametrized altsyncram(s) using Synopsys Design Compiler? Synopsys DC generates black boxes for which all parameters are skiped. Is there a solution to get the paramers into the netlist or is there a solution to automatically post process a netlist with quartus and/or Synplify to replace the black boxes in the netlist? ... unfortunately i have to go with Synopsys DC and can not skip DC Synthesis.   Thank you.

[Altera_Forum]

I haven't seen anyone use DC synthesis for many years. Note that Synopsys bought Synplify, so they do have an excellent FPGA synthesis tool. If there's something you need like DesignWare support, they might have that integrated. For whatever reason you need to use DC Synthesis, they might be able to provide a better solution that meets those needs. 

(As for why their parameters don't get passed to the netlist, I really don't know. If it's just RAMs, inferring them would probably be a better way to go all around, assuming Design Compiler can do this...)

[Altera_Forum]

Thank you for your answer.  

I'm not fimiliar with DesignWare. Is DesignWare able to execute DC-TCL-synthesis scripts? The reason why I have to stick with DC is because I have to do some changes in the netlist during synthesis. Therefore I source some synthesis scripts which require a GTECH-based netlist/design.

[Altera_Forum]

I believe DesignWare is a library of IP from Synopsys. I may have the name wrong. It won't help you, I was just mentioning it as a reason you need to keep with DC Compiler. Your reason makes sense.