Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Pin assignment error for DDR4 in quartus prime pro17.1

srinivasan
Beginner
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Hi,

   Error(14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 DQ_GRP(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error(175020): The Fitter cannot place logic DQ_GRP that is part of Generic Component ed_synth_emif_0 in region (148, 33) to (148, 44), to which it is constrained, because there are no valid locations in the region for logic of this type.
Info(14596): Information about the failing component(s):
Info(175028): The DQ_GRP name(s): emif_0|emif_0|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[1].lane_inst_DQ_GRP_1
Error(16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below:
Error(175005): Could not find a location with: DQ_X9 (1 location affected)
Info(175029): DQ_GRP containing AT5
Info(175015): The I/O pad emif_0_mem_mem_dq[8] is constrained to the location PIN_AK8 due to: User Location Constraints (PIN_AK8)
Info(14709): The constrained I/O pad is contained within a pin, which is contained within this DQ_GRP

 

 

 

can anyone give the solution for above error?

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