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Platform Designer BFM bug

Altera_Forum
Honored Contributor II
1,082 Views

Hi all, 

 

I have a little bug that is really annoying. Probably my fault because it seems very simple ! 

I open a Platform Designer project with my Quartus pro (version 17.1). 

I instantiate an Intel FPGA Avalon-MM Slave BFM. 

This slave must have a data width of 512 with 8 words of 64 bits (I have a board with DDR, and I simulate the communications on the Avalon bus, hence this large data width). 

When I create the slave, I fill the parameters correctly: 

- symbol width = 64 

- number of symbols = 8 

 

But the an error occurs : byteenable[8] must be 64 (data_width/8) 

And I perfectly agree with him but the byteenable signal is set to a length of 8. And I cannot change that. 

 

Any ideas ? 

 

Thanks ! 

Alban
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2 Replies
Altera_Forum
Honored Contributor II
81 Views

Just for the record, I got an answer from Altera support and the solution was indeed simple, but not clear. If you use the byteenable signal, the symbol width of the Avalon slave interface must stick to 8 bits. Hence, you have to play with the number of symbols of the BFM to cope with the length you need. In my case, instead of have 8 symbols of 64 bits, I had to go with 64 symbols of 8 bits.

Altera_Forum
Honored Contributor II
81 Views

the "byteenable" signal name is misleading, it should be "symbolenable". But AFAIK they always use 8 bit symbols in their design examples so it may never have occurred to them.

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