Port "devclrn" or "devpor" does not exist in primitive "dffeas" of instance "gen_dff[...]"

[ZaidSahawneh]

I am instantiating a large number of dffeas through generate statements and receive the following errors for what seems like every generation:

Error(16184): Port "devclrn" does not exist in primitive "dffeas" of instance "g0[9].g1.g3[0].DFFEAS_inst"
Error(16184): Port "devpor" does not exist in primitive "dffeas" of instance "g0[9].g1.g3[0].DFFEAS_inst"

I saw that this was apparently a bug for Arria devices and software 22.2 or earlier. https://www.intel.com/content/www/us/en/support/programmable/articles/000092114.html

Even though I am using a Stratix 10 and am not using HDMI, I hoped upgrading my version of Quartus would fix this. I upgraded Quartus Prime Pro from 21.1 to 22.3 but still received the error.

I am currently in the process of upgrading again to 24.3 but am not confident it will work. Is this in fact a bug? Or is there an error on my end? All of the library modules look correct.

I originally was working on Quartus 21.1 and Synthesizing for a Stratix 10 device. My design doesn't use HDMI.

[RichardTanSY_Altera]

Hi,

The error message indicate that;

CAUSE: You connected a port to the specified primitive through the specified port name, but the name does not exist.

ACTION: Make sure that you spelled the port name correctly and replace the port name with a legal primitive port name.

For further detail, please refer to the "Example 2–20. DFF Primitive Instantiation, Verilog HDL" in the Designing with Low-Level Primitives User Guide.

https://www.intel.com/content/www/us/en/content-details/654838/designing-with-low-level-primitives-user-guide.html?DocID=654838

If this error is caused by using an Intel/Altera IP, please share your design .qar file (Project > Archive Project) that can reproduce the issue.

This will allow me to escalate the matter to the IP specialist for further investigation.

Regards,

Richard Tan

[ZaidSahawneh]

I am instantiating these in a custom component. My instantiation reads as follows:

DFFEAS_inst : DFFEAS
port map
(
Q => f_signal(i)(j), -- Data output
CLK => i_clock, -- Clock input
ENA => '1', -- Clock enable input
D => i_sigin(j), -- Data input
SCLR => i_reset -- Synchronous reset input
--S => '0' -- Synchronous set input
);

I do not attempt to use any devclrn port or devpor port but still get the 'port devclrn does not exist in primitive "dffeas" ' / 'port devpor does not exist in primitive "dffeas" ' errors

I went ahead and added them thinking maybe making them explicit would help it connect them. The new instantiation reads as follows:

DFFEAS_inst : DFFEAS
port map
(
Q => f_signal(i)(j), -- Data output
CLK => i_clock, -- Clock input
ENA => '1', -- Clock enable input
D => i_sigin(j), -- Data input
SCLR => i_reset, -- Synchronous reset input
--S => '0' -- Synchronous set input
--+---------------------------------------------------------------------------
DEVCLRN => '1',
DEVPOR => '1'
);

I still get the same error.

The definition found in [quartus installation dir]/libraries/vhdl/alteradirectory/altera_primitives_components.vhd has both of those signals and the spelling is correct. not explicitly connecting them shouldn't cause an error especially since they have a default value. The definition of the primitive reads as follows:

component dffeas
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
dont_touch : string := "false";
x_on_violation : string := "on";
lpm_type : string := "DFFEAS";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*" );

port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '1';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic );
end component;

As you can see the spelling is correct and the signals exist in the primitive library definition. As well as the error occurs even when I do not use those ports.

My library calls read:

library ieee;
use ieee.std_logic_1164.all;
library altera;
use altera.altera_primitives_components.all;

[RichardTanSY_Altera]

Could you share me the .qar project that could duplicate the error?

I will need to further investigate.

Regards,

Richard Tan

[RichardTanSY_Altera]

Any update on this?

Do you able to share the project?

Regards,

Richard Tan

[ZaidSahawneh]

Apologies for the delay.

I cannot share the project but I think I can get a shell together that may do the same thing. I'll try to put it together this week or next. If I can't get one together that recreates the error then I will reply saying so and we can close this item then.

[RichardTanSY_Altera]

Sure. Do let me know once you able to create a simplified design that could duplicate the error.

Regards,

Richard Tan

[RichardTanSY_Altera]

Hi,

Do you able to share a simplified design to duplicate the error?

Regards,

Richard Tan

[ZaidSahawneh]

Apologies but due to time constraints I wasn't able to do that. For anyone skimming this thread, my solution was to just write my own flip flop and instantiate that instead.

[RichardTanSY_Altera]

Thank you for sharing your solution.

I understand your situation. In that case, do you need any further assistance from my side?

Regards,

Richard Tan

[ZaidSahawneh]

No more assistance is necessary at this time. Thank you.

[RichardTanSY_Altera]

Thank you for the confirmation.

Now, I will transitioning this thread to community support. If you have any further questions or concerns, please don't hesitate to reach out. Please login to https://supporttickets.intel.com/s/?language=en_US , view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support.

The community users will be able to help you on your follow-up questions.

Thank you and have a great day!

Best Regards,

Richard Tan