I've met a unexpected behaviour with my design and I just can't figure it out why.
First, I did some logic to detect the postive edge of input signal. Then I use the pulse to drive output signal to 'high'.
However, I've found the when reset being toggled, the output signal will also being toggled (one pulse) when input signal remains 'low'.
Do you have any idea if there is any casue could lead this situation?
The figure below is the waveform generated by SignalTap.
I've also attached my source code if you need it.
----- Source code----
// signal in positive edge detect
always @ (posedge clock) begin
if(!reset)
signal_in_r <= 1'b0;
else
signal_in_r <= signal_in;
end
wire signal_in_pulse;
assign signal_in_pulse = signal_in & ~signal_in_r;
// signal out logic
reg signal_out;
always @ (posedge clock) begin
if(!reset) begin
signal_out <= 1'b0;
end else if (signal_in_pulse) begin
signal_out <= 1'b1;
end
end
----- Source code----
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