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Power simulation

Altera_Forum
Honored Contributor II
‎08-11-2010 07:23 AM
1,088 Views

Hi. 

I have a design that I'd like to run through a power simulation before I actually program it into the device (Stratix III). I'd like to check some different operating modes of the design and see how it affects the power consumption (to be exact, I'd like to see which operating modes might damage the circuit). As I understood, it is possible to specify the exact design inputs through an output VCD file of the timing simulation, and use that file for an accurate power simulation of the FPGA. 

I ran a short simulation with all the chip's input and output ports and put the created VCD file into the PowerPlay analyzer input. After running the simulation I saw that the power estimation was about the same in comparison to running it without an input file (vectorless estimation). Looking in the report, under the "Confidence Metric Details" I see that the data source under "Simulation (from file)" is about 0.1%, and the data source under "Vectorless estimation" is 99.9%. That leads me to believe that the simulation didn't use the VCD file as much as I thought. 

Did I do something wrong?
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Altera_Forum
Honored Contributor II
‎08-15-2010 08:41 AM
363 Views

You should run a long simulation with realistic (or worst case condition) input data. 

Only in this case the .vcd file will reflect the realistic transition probabilities of the circuit. This will the lead to a more accurate estimation of the power dissipation (the dynamic component). 

Have you tried this?
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