Prevent instantiation of clock driver

Altera_Forum · ‎10-13-2016

Hi all,

to debug a design I have routed several clock signals to FPGA output pins (so that I can measure them). As a consequence, the compilation failed, because the fitter could not place one of the corresponding clock drivers:


Error (14986): After placing as many components as possible, the following errors remain:
Error (175001): The Fitter cannot place 1 global or regional clock driver.
Info (14596): Information about the failing component(s):
Info (175028): The global or regional clock driver name(s): cam_lsvds:cam_lsvds_1|altlvds_rx:ALTLVDS_RX_component|cam_lsvds_lvds_rx:auto_generated|cam_lsvds_altclkctrl:rx_outclock_buf|sd7

As this is only for debugging purposes I would like to disable the instantiation of a clock driver for this specific signals. Is this possible, maybe in the assignment editor?

Altera_Forum · ‎10-13-2016

PLL's can only drive globals. There is physically no way to have them use local routing. Something else will need to be demoted.

Altera_Forum · ‎10-13-2016

That's good to know, thank you!