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I have a design that uses two PLLs that drive separate clock output pins. Because the PLLs are identical and are driven from the same input clock, Quartus II is optimizing away one of the PLLs. I have reasons to want to keep both, and I want to know how to tell Quartus to keep the "redundant" PLL. I've tried the "synthesis keep" attribute but that only works for wires apparently. I could contrive the design to make it appear to Quartus that the PLLs are being used differently, but this seems silly and shouldn't be necessary. Does anyone know how to do this?
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--- Quote Start --- I have a design that uses two PLLs that drive separate clock output pins. Because the PLLs are identical and are driven from the same input clock, Quartus II is optimizing away one of the PLLs. I have reasons to want to keep both, and I want to know how to tell Quartus to keep the "redundant" PLL. I've tried the "synthesis keep" attribute but that only works for wires apparently. I could contrive the design to make it appear to Quartus that the PLLs are being used differently, but this seems silly and shouldn't be necessary. Does anyone know how to do this? --- Quote End --- Bring the clock in on seperate input pins. Kevin Jennings
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Yes, and I could also have the PLL resets handled differently between the two, but I was hoping to find a way to tell Quartus to just leave it alone.
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Found a fix for this:
Assignments->Settings->Fitter Settings->More Settings->Auto Merge PLLs It's on by default, which seems wrong since it's an optimization with side effects.- Mark as New
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--- Quote Start --- Found a fix for this: Assignments->Settings->Fitter Settings->More Settings->Auto Merge PLLs It's on by default, which seems wrong since it's an optimization with side effects. --- Quote End --- Can't find this option (Auto Merge PLLs) on specified way. My Quartus software version is 13.1. Could you tell me your software version?

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