Hi ,
I am trying to read a synthesized netlist into prime time, but it throws the following errors.
errors have been highlighted in red in the console output section Did anyone run into these kind of errors ? Kindly looking for help.
My Script:
set link_library lsi_10k.db
set target_library { lsi_10k.db }
read_verilog output/mips.v
current_design top
source const/mips.sdc
Console Output:
set link_library lsi_10k.db
lsi_10k.db
set target_library { lsi_10k.db }
lsi_10k.db
read_verilog output/mips.v
Loading verilog file '/DCNFS/users/student/aanbusel/mips/output/mips.v'
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current_design top
{"top"}
source const/mips.sdc
Information: Setting sdc_version outside of an SDC file has no effect (SDC-1)
Error: Cannot read link_path file 'lsi_10k.db'. (LNK-001)
Linking design top...
Warning: Unable to resolve reference to 'dataMemory' in 'top'. (LNK-005)
Information: Creating black box for regfileinst/reg_file... (LNK-043)
Warning: Module 'pc' in file '/DCNFS/users/student/aanbusel/mips/output/mips.v' is not used in the current design . (LNK-039)
Error: Library ports does not have a complete set of trip-point thresholds. (DBR-207)
Warning: Setting input delay on clock port (clk) relative to a clock (clk) defined at the same port. Command is ignored. (UITE-489)
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