Problem SDRAM....Burst Terminate!!!

[Altera_Forum]

Hi all, 

 Ok, I found out that SDRAM keeps writing forever and never stop, when I call IOWR_32DIRECT(...) in SignalTap.    When I look at Dev Board Cyclone II and it does show Write and Burst Terminate in SignalTap.   My board is Cyclone III with MT48LC4M32B2-7. Maybe clock phase shift or something else.   Thanks for read my post and help. Sean

[Altera_Forum]

spaugh, 

 I don't know. I found this sample from Stratix S260. It uses the same sdram MT48LC4M32B2-7 at 133 MHz and sys_clk at 100 MHz. My board uses CII with the same sdram, so that why I use it. But I can use the same clock rate for both.   ~Sean

[Altera_Forum]

Updated: 

 I don't know what the different on my old board vs new board. The new board seems to work little better.    Nios C code: volatile unsigned long w, r; unsigned int i;  for (i=5; i<20; i++) { IOWR_32DIRECT(SDRAM_BASE, i*4, i); printf("Write: %x\n", i);  usleep(1000); r = IORD_32DIRECT(SDRAM_BASE, i*4); printf(" Read: %x\n\n", r); }   // ****************** New board output: nios2-terminal: connected to hardware target using JTAG UART on cable nios2-terminal: "USB-Blaster [USB-0]", device 1, instance 0 nios2-terminal: (Use the IDE stop button or Ctrl-C to terminate)  Write: 5 Read: 5  Write: 6 Read: 6  Write: 7 Read: 7  Write: 8 Read: 8  Write: 9 Read: 9  Write: a Read: a  Write: b Read: b  Write: c Read: c  Write: d Read: d  Write: e Read: e  Write: f Read: f  Write: 10 Read: 10  Write: 11 Read: 11  Write: 12 Read: 12  Write: 13 Read: 13   Old board output: nios2-terminal: connected to hardware target using JTAG UART on cable nios2-terminal: "USB-Blaster [USB-0]", device 1, instance 0 nios2-terminal: (Use the IDE stop button or Ctrl-C to terminate)  Write: 5 Read: 0  Write: 6 Read: 0  Write: 7 Read: 0  Write: 8 Read: 0  Write: 9 Read: 0  Write: a Read: 0  Write: b Read: 0  Write: c Read: 0  Write: d Read: 0  Write: e Read: 0  Write: f Read: 0  Write: 10 Read: 0  Write: 11 Read: 0  Write: 12 Read: 0  Write: 13 Read: 0   ~Sean 

[Altera_Forum]

Hi all, 

 Good news. I get the board EP3C120 working with SDRAM great. My company downgrade from EP3C120 to EP3C80. I use Project/Revisions and create C80 and compile. But I coudn't get to run with SDRAM, so I look at pinout all SDRAM pins assigment are all the same, but there are some different pinouts between C120 and C80. My question is.    Can I force to use pinout from C120 to C80?   Thanks, Sean

[Altera_Forum]

Thanks all... 

 The problem is on EP3C80 hardware board. The SDRAM clock has so much noise signal, so my friend hardware will take a look at it.    When I put probe oscope on the clk bus, it works just fine but soon I remove the probe from clk line then it doesn't work anymore.   Thanks everyone and Happy New Year....   Sean