Problem about building LCD display with SOPC using DE0-nano

[Altera_Forum]

Hi everyone, I'm new using in Quartus. 

 Now I'm doing a project which displaying the xyz coordinates of the accelerometer on the DE0-Nano on the external LCD. And I need to SOPC builder to build the system as the project requied.    Firstly, I just want to make the LCD work, so I built a bacis SOPC with CPU, jtag_uart, SDRAM(8 MB), the builder-ready LCD module in SOPC and ALTPLL generated two clocks which are 50 Mhz system clock and 100 Mhz SDRAM clock with -2.5 ns phase shift.    After the SOPC is ready, I use EDS to run the hello world template to test the program. but there is an error keeps showing up, which says like below   Using cable "USB-Blaster [USB-0]", device 1, instance 0x00 Pausing target processor: OK Initializing CPU cache (if present) OK  Downloading 02000000 ( 0%) Downloaded 57KB in 0.9s (63.3KB/s)  Verifying 02000000 ( 0%) Verify failed between address 0x2000000 and 0x200E313 Leaving target processor paused   I think this means there is some thing wrong with the SDRAM, but I am not sure which part, so could anyone give me some clues about this? I will be very very appreciated.    I also attched some pictures about my system and SOPC which helps you to understand. 

[Altera_Forum]

could any help me? cheers

[Altera_Forum]

could anyone help me? cheers

[Altera_Forum]

--- Quote Start ---   Firstly, I just want to make the LCD work   --- Quote End ---    Reduce your complexity.  Build an SOPC system with a JTAG-to-Avalon-MM master and a PIO component and an LCD component. Connect the PIO component to LEDs on your board.  Then use SystemConsole to perform read/write access to your LEDs. When you can blink your LEDs, you know that you have SystemConsole working.  Then perform read/write accesses to the LCD.  The LCD needs to be initialized before you will see characters.  Per this thread: http://www.alteraforum.com/forum/showthread.php?t=29042  Use the Optrex manual as a reference:  http://www.optrex.com/pdfs/dmcman_full.pdf  Cheers, Dave

[Altera_Forum]

To ensure your memory interface is working properly I recommend creating a system with the following: 

 Nios II core JTAG debug module Biggest Onchip memory you can fit into the FPGA to serve up code JTAG UART SDRAM controller  Assuming you have enough onchip memory then you can use the mem_test_small application template in the Nios II EDS. Using a CPU is not a good stresstest but it can find address/data shorts sufficiently. If you don't have enough memory you can probably study that application and figure out ways to reduce the code footprint to the point where you can fit it into onchip memory.  My motto is "until you have tested your external memory, it doesn't work!". Just like Dave said, debug using small designs so that you can pinpoint the problem easier.

[Altera_Forum]

Thank you very much Dave and Omen, I am trying now.