Problem in designing multiple Queues

[Altera_Forum]

I need to design 300 queues. Each of the queues supports 2000 words with 8 bit/word. 

I declared 300 register arrays (reg[7:0] queue [1999:0]) and compiled in Quartus. I am getting an error message: design requires to many ram resources to fit in the selected device or any device in the device family. I am using stratixII device. I think it doesnot support that many queue in one fpga chip. Is there any way of making that many queues inside fpga?   I would really appreciate if anybody could help me with my design.  Francisco

[Altera_Forum]

If each of the 300 register arrays has to be independently addressable, then you have too many for Stratix II. If you can configure the arrays so that multiple arrays can be in a single large memory with at most two arrays in the memory accessed at any particular time (using the dual-port capability of the memory), then you could fit nearly that much memory into M-RAMs with the rest being in the smaller RAM blocks. 

 These are the calculations if each register array has to be independently addressable:  An M512 can be configured as 64x8. Each register array requires 2000/64 = 32 M512s.  An M4K can be configured as 512x8. Each register array requires 2000/512 = 4 M4Ks.  If each array is a single-clock single-port memory, then 2 arrays can be packed into a single M-RAM.  The EP2S180, the largest Stratix II device, has 930 M512s, 768 M4Ks, and 9 M-RAMs.  You can get 930/32 = 29 arrays into M512s, 768/4 = 192 arrays into M4Ks, and at most 9*2 = 18 into M-RAMs.  That adds up to 239 register arrays, well under the 300 you declared.

[Altera_Forum]

Thank you Brad for your reply. 

The queues have to be dual port and independantly addressable. I am not building real hardware for another month. So the best I can do at this point is reduce the word size by half for the synthesizing and testing. Once I have the prototyping board I guess I can build queue in external ram that comes with the board.  Do you have any other suggestion?

[Altera_Forum]

Hello, 

 also without knowing further design details, it seems obvious, that the said 300 queues can't operate fully parallel in the design, simply cause no FPGA would have several thousand pins needed to interface them independantly. Thus there must be some hidden redundancy here. Cause input and output signals obviously must be serialized or multiplexed somehow, this could be also be done for RAM resources.   The 300 queues may be logically independant, but some of them surely could share adresses. When using external memory (SSRAM seems best fitted here) it's the same: The logical queues have to be managed within physical memory. I guess, queue's access has an implicite multiplexing behaviour by definition, e. g. an address information that selects one of many for read or write. But queue managment scheme can't be discussed without knowing the nature of interface and requirements in detail.  Regards, Frank