Problem in simulation o/p of circular buffer

[Altera_Forum]

hello all, 

i tried to impelement a circular buffer in quartus II Code is compiled successfully,,but i am undable to view o/p in waveforms. Hers the code..  ---FIFO buffer  Library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity fifoeda is  generic (  B : natural :=8; -- number of bit  W: natural :=4 -- number of address bit );  port (   clk, reset : in std_logic;  rd, wr : in std_logic;  w_data : in std_logic_vector ( B-1 downto 0);  empty, full : out std_logic;  r_data : out std_logic_vector (B-1 downto 0) ); end fifoeda;  architecture arch of fifoeda is  type reg_file_type is array (2**W-1 downto 0) of std_logic_vector (B-1 downto 0);  --signal array_reg: reg_file_type;  signal w_ptr_reg, w_ptr_next, w_ptr_succ: std_logic_vector(W-1 downto 0);  signal r_ptr_reg, r_ptr_next, r_ptr_succ: std_logic_vector(W-1 downto 0);  signal full_reg, empty_reg, full_next, empty_next: std_logic;  signal wr_op: std_logic_vector ( 1 downto 0);  signal wr_en: std_logic; begin  --==============================================  --========register files=====  process(clk, reset)  variable array_reg : reg_file_type;  begin  if (reset='1') then  array_reg:= (others=>(others=>'0'));  elsif (clk'event and clk='1') then  if wr_en ='1' then  array_reg( to_integer( unsigned (w_ptr_reg))):=w_data;  end if;  end if;  --end process;  -- read port  r_data<= array_reg( to_integer(unsigned(r_ptr_reg)));  -- write enable only when FIFO is not full  end process;  wr_en<= wr and (not full_reg);  --===================================================  -- fifo control logic  --===================================================  -- register for read and write pointers  process( clk, reset)  begin  if ( reset= '1') then  w_ptr_reg <= (others=>'0');  r_ptr_reg <= (others=>'0');  full_reg <= '0';  empty_reg <= '1';  elsif (clk' event and clk='1') then  w_ptr_reg<= w_ptr_next;  r_ptr_reg <= r_ptr_next;  full_reg <= full_next;  empty_reg<= empty_next;  end if;  end process;   -- successive pointer values  w_ptr_succ<= std_logic_vector (unsigned(w_ptr_reg)+1);  r_ptr_succ<= std_logic_vector (unsigned (r_ptr_reg)+1);   -- next-state logic for read and write pointers  wr_op <= wr& rd;   process( w_ptr_reg, w_ptr_succ, r_ptr_reg, r_ptr_succ, wr_op, empty_reg, full_reg)   begin  w_ptr_next <= w_ptr_reg;  r_ptr_next<= r_ptr_reg;  full_next <= full_reg;  empty_next <= empty_reg;    Case wr_op is  when "00" => -- no op   when "01" => -- read  if ( empty_reg /='1') then -- not empty  r_ptr_next<= r_ptr_succ;  full_next <= '0';  if ( r_ptr_succ = w_ptr_reg) then  empty_next<= '1';  end if;  end if;  when "10" => -- write   if (full_reg /= '1') then -- not full  w_ptr_next <= w_ptr_succ;  empty_next<= '0';  if (w_ptr_succ = r_ptr_reg) then  full_next <= '1';  end if;  end if;  when others=> -- write /read;  w_ptr_next <= w_ptr_succ;  r_ptr_next <= r_ptr_succ;  end case;  end process;  ---==================out put=====  full<= full_reg;  empty <= empty_reg; end arch;   Can anyone help me to figure out bug ?? Thanks, Ksr

[Altera_Forum]

You dont say if the problem is in simulation or on FPGA. 

 I can see a massive problem with the first process - you have r_data assigned outside of a clock, plus it is also assigned from a variable. You cannot have output assigned like this in a process. You'll need to take it out from the process and put array_reg back as a signal like you had before.  Ive simulated it and it seems to work fine - I get output. Whats the problem you're getting?

[Altera_Forum]

@Tricky, 

sorry its my mistake..i posted the wrong one. At first i written that code and later changed it however.. Yes, my output is outside of the process and my array object is of signal type rather than variable type.  My prob. is in output waveform i am unable to view o/p in o/p as it is '0' all through input  and even full,empty signals are inactive.

[Altera_Forum]

update : 

Now i am geting partial o/p i.e., some of the input values are being read with "XX" in between them.:confused:   Is thr anyway to send my simulatioin waveform to u to figure out whts wrong?? or else let me know the input values that u used to view waveform..  Thanks, KSR.

[Altera_Forum]

"XX" ususally occurs when you are driving 2 signals on the same output, or being a bus, it could be that the bus is unitialised (ie - you're switching to something thats uninitialised. 

 To post the waveform, take a screenshot and make a jpg of it and post it here.  It might be good to post the code you're working with too - the UUT AND the testbench.

[Altera_Forum]

heres my output waveform.. 

as u can see the input values are appeared in on output port but some of the values got delayed more. Does this works for ring buffer..and what about full,empty signals??? btw..i got rid of those dontcare values...  Thanks a lot for giving me time...

[Altera_Forum]

somehow i lost the names of ports..well, i provide the names here.. 

sorry for inconvenience...  clk reset wr rd w_data(input) r_data(output) empty full  _____________________________  Library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity fifoeda is  generic (  B : natural :=8; -- number of bit  W: natural :=4 -- number of address bit );  port (   clk, reset : in std_logic;  rd, wr : in std_logic;  w_data : in std_logic_vector ( B-1 downto 0);  empty, full : out std_logic;  r_data : out std_logic_vector (B-1 downto 0) ); end fifoeda;  architecture arch of fifoeda is  type reg_file_type is array (2**W-1 downto 0) of std_logic_vector (B-1 downto 0);  signal array_reg: reg_file_type;  signal w_ptr_reg, w_ptr_next, w_ptr_succ: std_logic_vector(W-1 downto 0);  signal r_ptr_reg, r_ptr_next, r_ptr_succ: std_logic_vector(W-1 downto 0);  signal full_reg, empty_reg, full_next, empty_next: std_logic;  signal wr_op: std_logic_vector ( 1 downto 0);  signal wr_en: std_logic; begin  --==============================================  --========register files=====  process(clk, reset)  --variable array_reg : reg_file_type;  begin  if (reset='1') then  array_reg<= (others=>(others=>'0'));  elsif (clk'event and clk='1') then  if wr_en ='1' then  array_reg( to_integer( unsigned (w_ptr_reg)))<=w_data;  end if;  end if;  end process;  -- read port   r_data <= array_reg( to_integer(unsigned(r_ptr_reg)));   -- write enable only when FIFO is not full  --end process;  wr_en<= wr and (not full_reg);  --===================================================  -- fifo control logic  --===================================================  -- register for read and write pointers  process( clk, reset)  begin  if ( reset= '1') then  w_ptr_reg <= (others=>'0');  r_ptr_reg <= (others=>'0');  full_reg <= '0';  empty_reg <= '1';  elsif (clk' event and clk='1') then  w_ptr_reg<= w_ptr_next;  r_ptr_reg <= r_ptr_next;  full_reg <= full_next;  empty_reg<= empty_next;  end if;  end process;   -- successive pointer values  w_ptr_succ<= std_logic_vector (unsigned(w_ptr_reg)+1);  r_ptr_succ<= std_logic_vector (unsigned (r_ptr_reg)+1);   -- next-state logic for read and write pointers  wr_op <= wr& rd;   process( w_ptr_reg, w_ptr_succ, r_ptr_reg, r_ptr_succ, wr_op, empty_reg, full_reg)   begin  w_ptr_next <= w_ptr_reg;  r_ptr_next<= r_ptr_reg;  full_next <= full_reg;  empty_next <= empty_reg;    Case wr_op is  when "00" => -- no op   when "01" => -- read  if ( empty_reg /='1') then -- not empty  r_ptr_next<= r_ptr_succ;  full_next <= '0';  if ( r_ptr_succ = w_ptr_reg) then  empty_next<= '1';  end if;  end if;  when "10" => -- write   if (full_reg /= '1') then -- not full  w_ptr_next <= w_ptr_succ;  empty_next<= '0';  if (w_ptr_succ = r_ptr_reg) then  full_next <= '1';  end if;  end if;  when others=> -- write /read;  w_ptr_next <= w_ptr_succ;  r_ptr_next <= r_ptr_succ;  end case;  end process;  ---==================out put=====  full<= full_reg;  empty <= empty_reg; end arch;

[Altera_Forum]

--- Quote Start ---  heres my output waveform.. as u can see the input values are appeared in on output port but some of the values got delayed more. Does this works for ring buffer..and what about full,empty signals??? btw..i got rid of those dontcare values...  Thanks a lot for giving me time...  --- Quote End ---     From that diagram, I have no idea whats what.